Methods and apparatus for servicing commands through a memory controller port
View Patent ↗In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority; (2) receiving a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority; (3) determining whether the first and second commands will be serviced through the same memory port; and (4) if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period. Numerous other aspects are provided.
1. A method of servicing commands, comprising:
receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority;
receiving a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority;
determining whether the first and second commands will be serviced through the same memory port;
if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period; and
wherein the first command is a command from a queue of pending commands; and
the second command is a command received from a processor or from a scalability port of the memory controller, wherein the scalability port connects the memory controller to a second memory controller.
2. The method of claim 1 wherein determining whether the first and second commands will be serviced through the same memory port includes:
determining a memory port of the memory controller through which the first command will be serviced based on a real memory address associated with the first command; and
determining a memory port of the memory controller through which the second command will be serviced based on a real memory address associated with the second command.
3. The method of claim 1 further comprising:
converting a real memory address associated with the first command to a physical memory address associated with the first command; and
converting a real memory address associated with the second command to a physical memory address associated with the second command; and
converting the physical memory address associated with the first command to a DRAM address associated with the first command and converting the physical memory address associated with the second command to a DRAM address associated with the second command in parallel.
4. The method of claim 1 further comprising:
if the first and second commands will be serviced through the same memory port, servicing the second command during a first time period; and
servicing the first command during a second time period after the first time period.
5. The method of claim 1 wherein the first command is from a queue of pending commands; and further comprising, notifying the queue of pending commands whether the first command is selected for servicing.
6. The method of claim 1 further comprising determining whether respective memory ports through which the first and second commands will be serviced are available to receive a command; and
wherein if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period includes, if the first and second commands will not be serviced through the same memory port and respective ports through which the first and second commands will be serviced are available to receive a command, servicing the first and second commands during the same period.
7. The method of claim 1 wherein servicing a command through the memory port includes storing the command in a read queue of the memory port.
8. An apparatus for servicing commands, comprising:
request handler logic for receiving commands for servicing from at least one of a processor and a scalability port;
queue logic for receiving commands for servicing from at least one of the request handler logic and an input/output (I/O) port; and
a memory controller for interfacing with memory, including a plurality of memory ports, coupled to the request handler logic and the queue logic;
wherein the apparatus is configured to:
receive a first command for servicing in the memory controller, wherein the first command is of a first priority;
receive a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority;
determine whether the first and second commands will be serviced through the same memory port; and
if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period; and
wherein the first command is a command from a queue of pending commands included in the queue logic; and
the second command is a command received from a processor or from a scalability port of the memory controller, wherein the scalability port connects the memory controller to a second memory controller.
9. The apparatus of claim 8 wherein the apparatus is further configured to:
determine a memory port of the memory controller through which the first command will be serviced based on a real memory address associated with the first command; and
determine a memory port of the memory controller through which the second command will be serviced based on a real memory address associated with the second command.
10. The apparatus of claim 8 wherein the apparatus is further configured to:
convert a real memory address associated with the first command to a physical memory address associated with the first command; and
convert a real memory address associated with the second command to a physical memory address associated with the second command; and
convert the physical memory address associated with the first command to a DRAM address associated with the first command and converting the physical memory address associated with the second command to a DRAM address associated with the second command in parallel.
11. The apparatus of claim 8 wherein the apparatus is further configured to:
if the first and second commands will be serviced through the same memory port, servicing the second command during a first time period; and
servicing the first command during a second time period after the first time period.
12. The apparatus of claim 8 wherein the first command is from a queue of pending commands included in the queue logic; and
wherein the apparatus is further configured to notify the queue of pending commands whether the first command is selected for servicing.
13. The apparatus of claim 8 wherein the apparatus is further configured to:
determine whether respective memory ports through which the first and second commands will be serviced are available to receive a command; and
if the first and second commands will not be serviced through the same memory port and respective ports through which the first and second commands will be serviced are available to receive a command, service the first and second commands during the same period.
14. The apparatus of claim 8 wherein the apparatus is further configured to store a command in a read queue of a memory port.