Thin film transistor array panel and fabrication

1. A manufacturing method of a thin film transistor array panel comprising:

forming a gate line on a substrate;

forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line;

forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact;

forming a first photoresist pattern on the third conducting film;

etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask;

removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern;

etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and

etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

2. The method of claim 1 , wherein the Cl-containing gas is at least one selected from Cl 2 , HCl, CCl 4 , BCl 3 , and SiCl 2 H 2 .

3. The method of claim 2 , wherein the Cl-containing gas is Cl 2 and a flow ratio of the Cl 2 gas and the F-containing gas is 1:1 to 1:10.

4. The method of claim 2 , wherein the Cl-containing gas is HCl and a flow ratio of the HCl gas and the F-containing gas is 1:4 to 1:10.

5. The method of claim 1 , wherein the F-containing gas is SF 6 or CF 4 .

6. The method of claim 1 , wherein the etching of the exposed ohmic contact is performed under a pressure of 100 to 800 mT.

7. The method of claim 1 , wherein the first photoresist pattern comprises a first portion and a second portion having a thickness greater than that of the first portion.

8. The method of claim 7 , wherein the formation of the second photoresist pattern comprises removing the second portion.

9. The method of claim 1 , wherein the etching of the first, second, and third conducting films is performed by wet etching.