Secure supply of an integrated circuit

1. An integrated circuit having at least one first linear regulator for providing a supply voltage to an internal load from an external voltage, and comprising at least one capacitive switched-mode power supply circuit with one or several switched capacitances, in parallel with the first linear regulator and activated, at least in an operation phase of the integrated circuit, at the same time as the first linear regulator.

2. The circuit of claim 1 , wherein said phase corresponds to a phase in which a calculation processor contained by the load is active.

3. The circuit of claim 2 , wherein the switched-mode circuit is sized according to the difference in the integrated circuit power consumption between its average power consumption and its power consumption during calculations executed by the processor.

4. The circuit of claim 1 , wherein said switched-mode circuit is activated as soon as the current consumed by the load exceeds a threshold.

5. The circuit of claim 1 , wherein said switched-mode circuit is permanently active.

6. The circuit of claim 1 , wherein a second linear regulator, fast with respect to the first linear regulator, is interposed between a first supply terminal at the load and the respective outputs of the first linear regulator and of the switched-mode circuit.

7. The circuit of claim 6 , wherein said first linear regulator comprises a P-channel MOS transistor, in series with a first N-channel MOS transistor of the second linear regulator between a first terminal of application of the external voltage and a first supply terminal of the load, at least one second N-channel MOS transistor of the second linear regulator connecting an output terminal of the switched-mode circuit to said first supply terminal of the load.

8. The circuit of claim 1 , wherein the switched-mode circuit comprises several capacitors having their charge organized at least for some of them in parallel and having their discharge organized in series.

9. The circuit of claim 1 , wherein the switched-mode circuit is of chopper type.

10. The circuit of claim 1 , wherein at least one first additional linear regulator and at least one additional capacitive switched-mode circuit with one or several switched capacitances are interposed between a second supply terminal of the load and a second terminal of application of the external supply voltage.

11. The circuit of claim 10 , wherein a second additional linear regulator, fast with respect to the first additional linear regulator, is interposed between the second supply terminal of the load and the respective inputs of the first additional linear regulator and of the additional switched-mode circuit.

12. The circuit of claim 11 , wherein said second additional linear regulator comprises a first P-channel MOS transistor), in series with an N-channel MOS transistor of the first additional linear regulator between the second supply terminal of the load and the second terminal of application of the external voltage, a second P-channel MOS transistor of the second additional linear regulator connecting said second supply terminal of the load to an input terminal of the additional switched-mode circuit.

13. A method for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, consisting of supplying at least the integrated circuit from a supply voltage (Vps) external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.

14. The method of claim 13 , wherein said currents are combined, at least during a phase where the processor is activated.

15. The method of claim 13 , wherein said switched-mode circuit is activated when the current surged by the load exceeds a threshold.

16. The circuit of claim 13 , wherein said switched-mode circuit is permanently activated.