Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element

1. A nonvolatile memory array, comprising:

a plurality of bit lines and word lines; and

a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising:

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines;

wherein storing a logic state of the memory cell comprises applying an electrical current through the storage element; and

wherein a logic state of the bipolar programmable storage element is written by substantially concurrently applying a logic high voltage potential to the word line, applying a logic high voltage potential to one of the first and second bit lines, and applying a logic low voltage potential to another of the first and second bit lines, a polarity of a voltage potential across the first and second bit lines being indicative of the logic state to be written into the memory cell.

2. The memory array of claim 1 , wherein at least a subset of the memory cells are arranged such that a first one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in a first and second one of the memory cells and connected to the second source/drains of the metal-oxide-semiconductor devices in a third and fourth one of the memory cells, and a second one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in the third and fourth one of the memory cells, and the second source/drains of the metal-oxide-semiconductor devices in the first and second one of the memory cells, and wherein the gates of the first, second third and fourth one of the memory cells are connected to different word lines in the memory array.

3. The memory array of claim 1 , wherein the plurality of bit lines are arranged substantially parallel relative to one another.

4. The memory array of claim 1 , wherein the plurality of word lines are arranged substantially parallel relative to one another.

5. The memory array of claim 1 , wherein the bipolar programmable storage element comprises a magnetic tunnel junction device.

6. The memory array of claim 1 , wherein the bipolar programmable storage element comprises a transition-metal oxide.

7. A nonvolatile memory array, comprising:

a plurality of bit lines and word lines; and

a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising:

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines;

wherein storing a logic state of the memory cell comprises applying an electrical current though the storage element; and

wherein a logic state of the bipolar programmable storage element is read by substantially concurrently applying a logic high voltage potential to the word line, applying a logic low voltage potential to one of the first and second bit lines, applying a read voltage potential to and sensing a current on another of the first and second bit lines, a magnitude of the sensed current being indicative of the logic state of the memory cell.

8. The memory array of claim 7 , wherein at least a subset of the memory cells are arranged such that a first one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in a first and second one of the memory cells and connected to the second source/drains of the metal-oxide-semiconductor devices in a third and fourth one of the memory cells, and a second one of the bit lines is connected to the first terminals of the bipolar programmable storage elements in the third and fourth one of the memory cells, and the second source/drains of the metal-oxide-semiconductor devices in the first and second one of the memory cells, and wherein the gates of the first, second third and fourth one of the memory cells are connected to different word lines in the memory array.

9. The memory array of claim 7 , wherein the plurality of bit lines are arranged substantially parallel relative to one another.

10. The memory array of claim 7 , wherein the plurality of word lines are arranged substantially parallel relative to one another.

11. The memory array of claim 7 , wherein the bipolar programmable storage element comprises a magnetic tunnel junction device.

12. The memory array of claim 7 , wherein the bipolar programmable storage element comprises a transition-metal oxide.