IP Library Granted Patent US 7,397,113
Granted Patent B2
US 7,397,113 · App. 11/474,659 · Granted Jul 8, 2008

Semiconductor device

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Quick Facts
Patent No.
US 7,397,113
App. No.
11/474,659
Granted
Jul 8, 2008
Kind
B2
Abstract

A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Claims (14)

1. A semiconductor device, comprising:

a semiconductor element;

a die pad on which the semiconductor element is mounted;

a plurality of electrode terminals, each of which has a connecting portion electrically connected with the semiconductor element; and

a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each of the electrode terminals on an opposite side from a surface having the connecting portion is exposed from the sealing resin as an external terminal surface,

wherein a recess configured to suppress peeling of the electrode terminal and the sealing resin is formed on the surface of each of the electrode terminals with the connecting portion and has a circular shape at the surface, the recess being arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion.

2. The semiconductor device according to claim 1 , wherein the semiconductor element and the electrode terminals are arranged so as to have a space interval of 200 μm or more between the outer edge of the semiconductor element and the end portion of the electrode terminals facing the semiconductor element.

3. The semiconductor device according to claim 2 , wherein the recess is formed on the surface of each electrode terminals with the connecting portion only between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion.

4. The semiconductor device according to claim 1 , wherein each electrode terminal has an inclined portion or a step portion at an end face of a cross-sectional geometry so that an area of the surface with the connecting portion becomes larger than an area of the external terminal surface.

5. The semiconductor device according to claim 2 , wherein each electrode terminal has an inclined portion or a step portion at an end face of a cross-sectional geometry so that an area of the surface with the connecting portion becomes larger than an area of the external terminal surface.

6. The semiconductor device according to claim 1 , wherein an end portion of the electrode terminal facing the semiconductor element is shaped on a form of a circular arc.

7. The semiconductor device according to claim 2 , wherein an end portion of the electrode terminal facing the semiconductor element is shaped on a form of a circular arc.

8. The semiconductor device according to claim 3 , wherein an end portion of the electrode terminal facing the semiconductor element is shaped on a form of a circular arc.

9. The semiconductor device according to claim 1 , wherein a lower surface of the electrode terminal directly opposite the recess forms an external terminal for the semiconductor device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2016
From: PANASONIC CORPORATION
To: MICRO-OPTIMUS TECHNOLOGIES, INC.
Reel/Frame 040724/0373 →