Acquisition method and apparatus for carrying out the method

1. A communications acquisition method, which comprises:

correlating a received binary-coded spread sequence with a frequency f and having m bits with a locally generated spread sequence by phase-shifting a multiplicity of locally generated spread sequences with respect to the received spread sequence;

storing the received spread sequence and processing the stored, received spread sequence at an oversampling rate of i*f, where i is an integer;

splitting the stored, received spread sequence into i sections and carrying out the correlation in i steps;

shifting the received spread sequence bit by bit within k cycles in k section variants each having m bits at an oversampling rate of k*f, where k is an integer, by shifting a most significant bit of a section variant to a position of a least significant bit of a succeeding section variant;

after k cycles, replacing the least significant bit by a succeeding bit of the received spread sequence and repeating the shifting and replacing steps m−1 times;

subdividing the locally generated spread sequence into k sections each having n bits, where n is an integer, and comparing each of these sections with a section variant of the received spread sequence within a cycle;

counting all matches and storing the count results; and

carrying out a maximum search over all the count results.

2. The method according to claim 1 , wherein a number of sections of prescribed length is k=32 and a chip length of the sections is n=32.

3. The method according to claim 1 , which further comprises:

summing the correlation results obtained per section correlation step over k section correlation steps to obtain a count result;

repeating the shifting step m−1 times for obtaining m−1 count results; and

carrying out a maxmum search over all the m count results.

4. The method according to claim 3 , wherein a number of sections of prescribed length is k=32 and a chip length of the section is n=32.

5. The method according to claim 1 , wherein the oversampling rate is 32 MHz.

6. A correlator for performing a communications acquisition, comprising:

a data memory having a memory input and a memory output, said FIFO memory inputting and outputting a content;

a shift register with feedback for holding a received signal sequence in serial form, said shift register being clocked at an oversampling rate and having register positions connected in parallel to said memory input for parallel storage of a plurality of shift register contents read out in succession, said memory output being connected in parallel with said register positions for parallel transfer of data to said shift register;

a further memory for holding reference signal sequences; and

a comparator for comparing the content of said data memory with a content of said further memory at said oversampling rate,

wherein the correlator further comprising means for correlating a received binary-coded spread sequence with a frequency f and having m bits with a locally generated spread sequence by phase-shifting a multiplicity of locally generated spread sequences with respect to the received spread sequence.

7. The correlator according to claim 6 , wherein the correlator further comprising means for storing the received spread sequence and process the stored, received spread sequence at said oversampling rate equal to i*f, where i is an integer.

8. The correlator according to claim 6 , wherein the correlator further comprising means for splitting the stored, received spread sequence into i sections and carry out the correlation in i steps.

9. The correlator according to claim 6 , wherein said comparator has a comparator output, and includes an adder comprising two-bit adders configured to form a cascaded interconnection, each of said two-bit adders having at least two inputs and an output, said output of each of said two-bit adders connected to one of said at least two inputs of a succeeding one of said two-bit adders, and said adder connected to said comparator output and configured to add up logic values produced during bit-by-bit comparison for matching bit positions.

10. A correlator for performing a communications acquisition, comprising:

a data memory having a memory input and a memory output, said FIFO memory inputting and outputting a content;

a shift register with feedback for holding a received signal sequence in serial form, said shift register being clocked at an oversampling rate and having register positions connected in parallel to said memory input for parallel storage of a plurality of shift register contents read out in succession, said memory output being connected in parallel with said register positions for parallel transfer of data to said shift register;

a further memory for holding reference signal sequences; and

a comparator for comparing the content of said data memory with a content of said further memory at said oversampling rate,

wherein the correlator further comprising:

means for correlating a received binary-coded spread sequence with a frequency f and having m bits with a locally generated spread sequence by phase-shifting a multiplicity of locally generated spread sequences with respect to the received spread sequence;

means for storing the received spread sequence and process the stored, received spread sequence at said oversampling rate equal to i*f, where i is an integer; and

means for splitting the stored, received spread sequence into i sections and carry out the correlation in i steps.

11. The correlator according to claim 10 , wherein said comparator has a comparator output, and includes an adder comprising two-bit adders configured to form a cascaded interconnection, each of said two-bit adders having at least two inputs and an output, said output of each of said two-bit adders connected to one of said at least two inputs of a succeeding one of said two-bit adders, and said adder connected to said comparator output and configured to add up logic values produced during bit-by-bit comparison for matching bit positions.