PLI-less co-simulation of ISS-based verification systems in hardware simulators

1. A method for providing verification for a simulation design, comprising:

obtaining the simulation design comprising a programming language interface system call;

obtaining a reference value corresponding to the programming language interface system call;

encoding the reference value into the simulation design to obtain a modified simulation design, comprising:

obtaining a set of hardware state elements from the simulation design;

obtaining a set of high-level state elements from a high-level design;

determining a common set of state elements from the set of hardware state elements and the set of high-level state elements;

identifying at least one relationship between the high-level state element and the hardware state element in the common set of state elements;

determining whether the at least one relationship is influenced by a test vector to obtain an influenced set of relationships; and

encoding the influenced set of relationships to obtain the modified simulation design, comprising:

obtaining high-level state element values for the high-level state elements in the influenced set of relationships from a simulation of the high-level design, and

storing the high-level state element values in an array, wherein at least one of the high-level state element values is the reference value;

compiling the modified simulation design to obtain a compiled simulation design; and

verifying the compiled simulation design using a simulation test bench.

2. The method of claim 1 , wherein the simulation design comprises a register transfer level design.

3. The method of claim 1 , wherein the high-level state element comprises at least one from the group consisting of a processor register and a memory.

4. The method of claim 1 , wherein the hardware state element comprises at least one from the group consisting of a flip-flop, a latch, and a memory.

5. The method of claim 1 , wherein the relationship comprises at least one of the group consisting of a one-to-one relationship, a one-to-many relationship, and a relationship defined by a mathematical function.

6. The method of claim 1 , wherein the compiled simulation design is verified on a hardware-based simulation test bench.

7. A computer system for providing verification for a simulation design, comprising:

a processor;

a memory;

a storage device; and

software instructions stored in the memory for enabling the computer system to perform:

obtaining the simulation design comprising a programming language interface system call;

obtaining a reference value corresponding to the programming language interface system call;

encoding the reference value into the simulation design to obtain a modified simulation design, comprising:

obtaining a set of hardware state elements from the simulation design;

obtaining a set of high-level state elements from a high-level design;

determining a common set of state elements from the set of hardware state elements and the set of high-level state elements;

identifying at least one relationship between the high-level state element and the hardware state element in the common set of state elements;

determining whether the at least one relationship is influenced by a test vector to obtain an influenced set of relationships; and

encoding the influenced set of relationships to obtain the modified simulation design, comprising:

obtaining high-level state element values for the high-level state elements in the influenced set of relationships from a simulation of the high-level design, and

storing the high-level state element values in an array, wherein at least one of the high-level state element values is the reference value;

compiling the modified simulation design to obtain a compiled simulation design; and

verifying the compiled simulation design using a simulation test bench.

8. The computer system of claim 7 , wherein the simulation design comprises a register transfer level design.

9. The computer system of claim 7 , wherein the high level state element comprises at least one from the group consisting of a processor register and a memory.

10. The computer system of claim 7 , wherein the hardware state element comprises at least one from the group consisting of a flip-flop, a latch, and a memory.

11. The computer system of claim 7 , wherein the relationship comprises at least one of the group consisting of a one-to-one relationship, a one-to-many relationship and a relationship defined by a mathematical function.

12. The computer system of claim 7 , wherein the modified simulation design is verified on a hardware-based simulation test bench.

13. Apparatus providing verification for a simulation design, comprising:

means for obtaining the simulation design comprising a programming language interface system call;

means for obtaining a reference value corresponding to the programming language interface system call;

means for encoding the reference value into the simulation design to obtain a modified simulation design, comprising:

means for obtaining a set of hardware state elements from the simulation design;

means for obtaining a set of high-level state elements from a high-level design;

means for determining a common set of state elements from the set of hardware state elements and the set of high-level state elements;

means for identifying at least one relationship between the high-level state element and the hardware state element in the common set of state elements;

means for determining whether the at least one relationship is influenced by a test vector to obtain an influenced set of relationships; and

means for encoding the influenced set of relationships to obtain the modified simulation design, comprising:

obtaining high-level state element values for the high-level state elements in the influenced set of relationships from a simulation of the high-level design, and

storing the high-level state element values in an array, wherein at least one of the high-level state element values is the reference value;

means for compiling the modified simulation design to obtain a compiled simulation design; and

means for verifying the compiled simulation design using a simulation test bench.

14. The apparatus of claim 13 , wherein the simulation design comprises a register transfer level design.