Pulse generating circuit, electronic device using this pulse generating circuit, cellular phone set, personal computer, and information transmitting method using this circuit
A pulse generating circuit includes a plurality of delay elements cascaded so as to constitute a predetermined loop, wherein when a predetermined input pulse is supplied to a leading end of the series connection, an effective frequency multiplication is applied to signals which appear at a plurality of portions out of the node portions among the plurality of delay elements and the terminal end portion of the series connection by a logical circuit to obtain an output pulse having a higher frequency than the input pulse.
1. A pulse generating circuit comprising:
a plurality of serially-connected delay elements that receives an input trigger pulse;
a plurality of logic elements that each communicate with at least one of the plurality of delay elements and that generate a first output pulse having a pulse width based in part on an output of the at least one of the plurality of delay elements; and
a logic circuit that receives the first output pulses from the plurality of logic elements and generates a discontinuous pulse train that includes a second output pulse.
2. The pulse generating circuit of claim 1 wherein the pulse width of each of the first output pulses is based in part on a delay time between a rising point of an input and a drop point of the output of the at least one of the plurality of delay elements.
3. The pulse generating circuit of claim 1 wherein the plurality of delay elements includes a plurality of cascaded inverter circuits.
4. The pulse generating circuit of claim 1 wherein the plurality of logic elements includes at least one logical AND gate.
5. The pulse generating circuit of claim 1 wherein at least one of the plurality of delay elements and the plurality of logic elements includes a CMOS current mode logic circuit.
6. The pulse generating circuit of claim 1 further comprising:
a comparator circuit that compares a delay of the plurality of delay elements to a reference delay; and
a control circuit that controls a delay of each of the plurality of delay elements based on an output of the comparator circuit.
7. The pulse generating circuit of claim 1 wherein each of the plurality of delay elements includes a CMOS inverter that receives a controlled current.
8. The pulse generating circuit of claim 1 wherein each of the plurality of delay elements includes a buffer circuit having a CMOS current mode logic circuit that receives a current and a delay of each of the plurality of delay elements is variably based on the current.
9. The pulse generating circuit of claim 1 further comprising:
an oscillation circuit having an oscillation frequency that includes at least one delay element; and
a phase-locked loop that includes the oscillation circuit, that compares an output of the oscillation circuit to a reference frequency, and controls a delay of the delay element based on the comparison,
wherein a delay of at least one of the plurality of delay elements is based on the comparison.
10. The pulse generating circuit of claim 1 further comprising:
a switching unit that connects an output of at least one of the plurality of delay elements to an input of the plurality of delay elements to form a ring oscillation circuit; and
a phase-locked loop that includes the ring oscillation circuit, wherein:
the pulse generating circuit locks the phase-locked loop to a reference frequency and generates a control signal that determines a delay of the at least one of the plurality of delay elements; and
the delay of the at least one of the plurality of delay elements is determined when the phase-locked loop is locked.
11. A cellular telephone comprising the pulse generating circuit of claim 1 .
12. A personal computer comprising the pulse generating circuit of claim 1 .
13. A pulse generating circuit comprising:
a delay circuit cascaded in N+1 stages each including a respective delay element; and
a switching unit that connects to a first potential level when an output of an i th stage of the delay circuit ANDed with an output of an i+1 th stage of the delay circuit is true, that connects to a second potential level when an output of the i+1 th stage of the delay circuit ANDed with an output of an i+2 th stage of the delay circuit is true, and that connects to a third potential level when neither of the outputs is true,
wherein N is a positive odd integer and 1≦i≦N−1.
14. The pulse generating circuit of claim 13 wherein each of the N+1 stages includes at least one MOS inverter and a unit that controls a source current of the MOS inverter and a delay of the delay circuit is based on the source current.
15. A pulse generating method comprising:
receiving an input trigger pulse at a plurality of serially-connected delay elements;
generating first output pulses having a pulse width based in part on an output of at least one of the plurality of delay elements at a plurality of logic elements;
receiving the first output pulses from the plurality of logic elements at a logic circuit; and
generating a discontinuous pulse train that includes a second output pulse at the logic circuit.
16. The method of claim 15 wherein the pulse width of each of the first output pulses is based in part on a delay time between a rising point of an input and a drop point of the output of the at least one of the plurality of delay elements.
17. The method of claim 15 wherein the plurality of delay elements includes a plurality of cascaded inverter circuits.
18. The method of claim 15 wherein the plurality of logic elements includes at least one logical AND gate.
19. The method of claim 15 wherein at least one of the plurality of delay elements and the plurality of logic elements includes a CMOS current mode logic circuit.
20. The method of claim 15 further comprising:
comparing a delay of the plurality of delay elements to a reference delay; and
controlling a delay of each of the plurality of delay elements based on the comparison.
21. The method of claim 15 wherein each of the plurality of delay elements includes a CMOS inverter that receives a controlled current.
22. The method of claim 15 wherein each of the plurality of delay elements includes a buffer circuit having a CMOS current mode logic circuit that receives a current and a delay of each of the plurality of delay elements is variably based on the current.
23. The method of claim 15 further comprising:
generating an oscillation frequency at an oscillation circuit that includes at least one delay element; and
comparing an output of the oscillation circuit to a reference frequency at a phase-locked loop; and
controlling a delay of the delay element of the oscillation circuit based on the comparison,
wherein a delay of at least one of the plurality of delay elements is based on the comparison.
24. The method of claim 15 further comprising:
connecting an output of at least one of the plurality of delay elements to an input of the plurality of delay elements to form a ring oscillation circuit;
locking a phase-locked loop to a reference frequency;
generating a control signal that determines a delay of the at least one of the plurality of delay elements; and
determining the delay of the at least one of the plurality of delay elements when the phase-locked loop is locked.
25. A pulse generating circuit comprising:
a plurality of serially-connected delay elements form a ring oscillator and oscillate at a first frequency;
a plurality of logic elements that each communicate with at least one of the plurality of delay elements and that generate a first output pulse having a pulse width based in part on an output of the at least one of the plurality of delay elements; and
a logic circuit that receives the first output pulses from the plurality of logic elements and generates a second output pulse having a second frequency that is greater than the first frequency.