Nonvolatile semiconductor storage device
View Patent ↗A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
1. A nonvolatile semiconductor memory device comprising:
a source node;
a drain node; and
a memory cell including a transistor and a device adapted to memorize information, both the transistor and the device being provided between the source node and the drain node;
wherein the memory cell is adapted to be programmed or erased when charges accumulated in the source node or the drain node are passed between the drain node and the source node.
2. A nonvolatile semiconductor memory device according to claim 1 ,
wherein the charges are accumulated in a bit line and the charges are accumulated in stray capacitance of the bit line.
3. A nonvolatile semiconductor memory device according to claim 1 ,
further comprising a capacitor connected to a bit line;
wherein the charges are accumulated in the capacitor.
4. A nonvolatile semiconductor memory device comprising:
a memory cell including a first transistor and a device adapted to memorize information;
a bit line connected to one side of a source or drain region of the first transistor in the memory cell; and
a source line connected to the memory cell;
wherein the memory cell is adapted to be programmed or erased by passing charges accumulated in the bit line to the device.
5. A nonvolatile semiconductor memory device according to claim 4 ,
further comprising a word line including a gate electrode of the first transistor.
6. A nonvolatile semiconductor memory device according to claim 4 ,
wherein the charges are accumulated in the bit line and the charges are accumulated in stray capacitance of the bit line.
7. A nonvolatile semiconductor memory device according to claim 4 ,
further comprising a capacitor connected to the bit line;
wherein the charges are accumulated in the capacitor.
8. A nonvolatile semiconductor memory device according to claim 4 , further comprising:
a control circuit adapted to generate a voltage to be applied to the bit line; and
a second transistor to connect the control circuit and the bit line;
wherein the charges are accumulated in the bit line by the second transistor cutting off.