Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
1. A field effect transistor, comprising:
a gate stack disposed upon an SOI substrate;
a trench formed in a top silicon layer of the SOI substrate, the trench contacting a buried insulator layer and undercutting the gate stack to define a gate-masked silicon channel;
a lateral silicon residue of the top silicon layer adjacent to the trench and opposite the gate-masked silicon channel; and
an epitaxial layer disposed in the trench, the epitaxial layer in contact with both the gate-masked silicon channel and the lateral silicon residue.
2. The field effect transistor according to claim 1 , wherein the epitaxial layer has a thickness in a range from about 100 Å to about 1,500 Å, and wherein the epitaxial layer is an n-doped layer or a p-doped layer and wherein the epitaxial layer has a top surface with a higher elevation than a top surface of the gate-masked silicon channel.
3. The field effect transistor according to claim 1 , wherein the epitaxial layer has a thickness in a range from about 100 Å to about 1,500 Å and further including:
a salicided raised epitaxial tip disposed in the epitaxial layer and adjacent to the gate stack.
4. The field effect transistor according to claim 1 , wherein the epitaxial layer has a thickness in a range from about 100 Å to about 1,500 Å, wherein the epitaxial layer is an n-doped layer or a p-doped layer, and further including:
a salicided polysilicon gate layer disposed above and on the gate stack.
5. The field effect transistor according to claim 1 , wherein the epitaxial layer has a thickness in a range from about 100 Å to about 1,500 Å, wherein the epitaxial layer is an n-doped layer or a p-doped layer, and further including:
a salicided raised epitaxial tip disposed in the epitaxial layer and adjacent to the gate stack; and
a salicided polysilicon gate layer disposed above and on the gate stack.
6. The field effect transistor according to claim 1 , wherein the gate stack includes a polysilicon gate electrode with a width, W, and wherein the gate-masked silicon channel includes a channel length less than width, W.
7. The field effect transistor according to claim 1 , wherein the gate stack includes a polysilicon gate electrode with a width, W, and wherein the gate-masked silicon channel includes a channel length in a range from about 0.2 W to about 0.99 W.
8. The embedded source/drain silicon-on-oxide (SOI) junction according to claim 1 , wherein the epitaxial layer comprises germanium.
9. The embedded source/drain silicon-on-oxide (SOI) junction according to claim 1 , further including:
a SOI channel embedded beneath the gate stack, wherein the gate stack includes a metal gate electrode with a width, W, and wherein the SOI channel includes a channel length less than width, W.
10. The field effect transistor of claim 1 , wherein the epitaxial layer has substantially the same crystal orientation as the gate-masked silicon channel and the lateral silicon residue.
11. The field effect transistor of claim 1 , wherein the epitaxial layer includes a closure seam between the gate-masked silicon channel and the lateral silicon residue and wherein the epitaxial layer substantially covers the buried insulator layer at the bottom of the trench.