Data processing unit
View Patent ↗A system and method for frame detection and generation. Each incoming clock-data stream is divided into two independent data streams: a clock path which preserves the timing of the individual clock domains and a data path which multiplexes an arbitrary number of data streams onto a parallel path. A framer array structure implements a context swap and synchronizes the data streams.
1. A method for processing data, comprising:
receiving a combined clock-data stream according to a first clock domain, the combined clock-data stream including both clock signals and data signals;
dividing the combined clock-data stream into an independent clock stream and an independent data stream;
synchronizing the independent data stream to a second clock domain for processing by a data processor, the second clock domain being different from the first clock domain;
preserving a timing of the independent clock stream according to the first clock domain during processing of the independent data stream by the data processor;
recombining the independent clock stream and the processed independent data stream to form a recombined clock-data stream; and
re-synchronizing the recombined clock-data stream to the first clock domain.
2. The method of claim 1 , wherein synchronizing the independent data stream to a second clock domain for processing by a data processor includes synchronizing the independent data stream to a second clock domain for processing by a framer state machine.
3. The method of claim 2 , further comprising aligning n-bits of the independent data stream onto a m-bit data bus for processing by the framer state machine, where m and n are integers, and m>n.
4. The method of claim 3 , wherein aligning n-bits of the independent data stream onto the m-bit data bus includes detecting whether a frame boundary of an incoming frame associated with the independent data stream is misaligned with respect to data transferred onto the m-bit data bus, and if the frame boundary is misaligned then aligning time slots of incoming frames onto the m-bit data bus.
5. The method of claim 4 , wherein aligning time slots of incoming frames onto the m-bit data bus includes aligning p-bits of the independent data stream onto the m-bit data bus in subsequent data transfers until a given frame boundary is aligned with respect to a given time slot, wherein p is an integer, p>n and p≦m.
6. The method of claim 5 , wherein n=8 and m=p=9.
7. The method of claim 2 , wherein processing the independent data stream includes loading from a memory device and storing to a memory device context information associated with the independent data stream.
8. The method of claim 7 , wherein processing the independent data stream further includes inserting an alarm or a framing pattern into the independent data stream.
9. A data processing system, comprising:
a clock-data pair to receive a combined clock-data stream according to a first clock domain, the combined clock-data stream including both clock signals and data signals;
a clock branch and a data branch to divide the combined clock-data stream into an independent clock stream and an independent data stream, the clock branch to preserve a timing of the independent clock stream according to the first clock domain during processing of the independent data stream by a data processor;
a first synchronizer to synchronize the independent data stream to a second clock domain for processing by the data processor, the second clock domain being different from the first clock domain;
a combiner to recombining the independent clock stream and the processed independent data stream to form a recombined clock-data stream; and
a second synchronizer to re-synchronizing the recombined clock-data stream to the first clock domain.
10. The system of claim 9 , wherein the data processor is a framer state machine.
11. The system of claim 10 , wherein the framer state machine aligns n-bits of the independent data stream onto a m-bit data bus for processing of the independent data stream, where m and n are integers, and m>n.
12. The system of claim 11 , wherein the framer state machine further detects whether a frame boundary of an incoming frame associated with the independent data stream is misaligned with respect to data transferred onto the m-bit data bus, and if the frame boundary is misaligned then the framer state machine aligns time slots of incoming frames onto the m-bit data bus.
13. The system of claim 12 , wherein the framer state machine aligns time slots of incoming frames onto the m-bit data bus including aligning p-bits of the independent data stream onto the m-bit data bus in subsequent data transfers until a given frame boundary is aligned with respect to a given time slot, wherein p is an integer, p>n and p≦n.
14. The system of claim 13 , wherein n=8 and m=p=9.
15. The system of claim 11 , wherein the framer state machine processes the independent data stream including loading from a memory device and storing to a memory device context information associated with the independent data stream.
16. The system of claim 15 , wherein the framer state machine further processes the independent data stream including inserting an alarm or a framing pattern into the independent data stream.
17. A data processing system, comprising:
means for receiving a combined clock-data stream according to a first clock domain, the combined clock-data stream including both clock signals and data signals;
means for dividing the combined clock-data stream into an independent clock stream and an independent data stream;
means for synchronizing the independent data stream to a second clock domain for processing by a data processor, the second clock domain being different from the first clock domain;
means for preserving a timing of the independent clock stream according to the first clock domain during processing of the independent data stream by the data processor;
means for recombining the independent clock stream and the processed independent data stream to form a recombined clock-data stream; and
means for re-synchronizing the recombined clock-data stream to the first clock domain.
18. The system of claim 17 , wherein the means for synchronizing the independent data stream to a second clock domain for processing by a data processor includes means for synchronizing the independent data stream to a second clock domain for processing by a framer state machine.
19. The system of claim 18 , further comprising means for aligning n-bits of the independent data stream onto a m-bit data bus for processing by the framer state machine, where m and n are integers, and m>n.
20. The system of claim 19 , wherein the means for aligning n-bits of the independent data stream onto the m-bit data bus includes means for detecting whether a frame boundary of an incoming frame associated with the independent data stream is misaligned with respect to data transferred onto the m-bit data bus, and if the frame boundary is misaligned then the means for aligning aligns time slots of incoming frames onto the m-bit data bus.