Granted Patent B2

US 7,500,021 · App. 10/849,958 · Granted Mar 3, 2009

Assignee: Fujitsu Microelectronics

Abstract

Claims (73)

1. An operation mode control circuit in a microcomputer, resettable by a reset signal from the outside, for performing processes under the control of a control program, the operation mode control circuit comprising:

a control signal generator for generating a first output signal, being output during a first subsequence for a reset of the microcomputer and for generating a second output signal for setting an operation mode of an input and output circuit;

a write protection circuit for generating a buffer signal in response to a first signal of the first output signal; and

a control circuit for latching the a second output signal from the control signal generator in response to the buffer signal from the write protection circuit,

wherein the control circuit sets an operation mode of an input and output circuit, which receives a signal from and sends a signal to the outside, in accordance with the latched second output signal,

wherein the write protection circuit comprises:

buffer units for outputting a buffer signal that is a buffered version of a first signal of the first output signal and outputting a fixed logical value signal in response to the first output signal excluding the first signal of the first out put signal output from the control signal generator; and

latch units for performing a latch process in response to the first output signal from the control signal generator and for outputting a status signal indicating a latch status thereof,

wherein the buffer units has an input terminal for receiving the status signal from the latch units, and outputs the fixed logical value signal if the status signal indicates the latch status, or outputs the buffer signal if the status signal does not indicate the latch status.

2. An operation mode control circuit in a microcomputer, resettable by a reset signal from the outside, for performing processes under the control of a control program, the operation mode control circuit comprising:

a control signal generator for generating a first output signal, being output during a first subsequence for a reset of the microcomputer and for generating a second output signal for setting an operation mode of an input and output circuit;

a write protection circuit for generating a buffer signal in response to a first signal of the first output signal; and

a control circuit for latching the a second output signal from the control signal generator in response to the buffer signal from the write protection circuit,

wherein the control circuit sets an operation mode of an input and output circuit, which receives a signal from and sends a signal to the outside, in accordance with the latched second output signal,

wherein the write protection circuit comprises:

an AND gate for receiving the first output signal from the control signal generator at one of input terminals thereof;

a flip-flop, with a reset terminal and a clock terminal thereof connected to an output terminal of the AND gate, for outputting a signal having a logical signal “0” when the reset signal is received at the reset terminal and for outputting a signal having a logical signal “1” when a pulse signal is received at the clock terminal thereof; and

a buffer for outputting a logically inverted version of a signal from the flip-flop to the other of the input terminals of the AND gate,

wherein the AND gate AND gates the first output signal from the control signal generator and the logically inverted version of the signal from the flip-flop.

3. An operation mode control circuit in a microcomputer for performing processes under the control of a control program, the operation mode control circuit comprising:

a control signal generator for generating a first output signal output during a first subsequence for a reset of the microcomputer, for generating a second output signal for setting an operation mode of an input and output circuit and for generating a first decode signal and a second decode signal;

a write protection circuit for generating a buffer signal that is a buffered version of a the first output signal from the control signal generator only if the first decode signal having predetermined data and the second decode signal having predetermined data have been successively received from the control signal generator; and

a control circuit for latching a second signal from the control signal generator in response to the buffer signal from the write protection circuit,

wherein the control circuit sets, in response to the second output signal latched, the operation mode of an input and output control circuit that receives a signal from and sends a signal to the outside,

wherein the write protection circuit comprises:

a decoder for outputting a first selection status signal and a second selection status signal in response to the first decode signal and the second decode signal from the control signal generator, respectively;

a first AND gate for receiving the first selection status signal at one of input terminals thereof, the first AND gate AND gating the first election status signal and the third output signal;

a second AND gate for receiving the second selection status signal at one of input terminals thereof, the second AND gate AND gating the second selection status signal and the first data;

a third AND gate for AND gating the second data and the first output signal;

a first flip-flop for latching an output signal from the first AND gate in response to the first output signal from the control signal generator and for outputting first data to the other of the input terminals of the second AND gate;

a second flip-flop for latching an output from the second AND gate in response to the first output signal from the control signal generator and for outputting second data to one of input terminals of the third AND gate; and

a buffer for outputting, to the other of the input terminals of the first AND gate, a third output signal that is a logically inverted version of the second data, wherein the control circuit includes a third flip-flop that latches the second output signal from the control signal generator in response to an output signal from the third AND gate.

4. An operation mode control circuit, in a microcomputer, resettable by a reset signal from the outside, for performing processes under the control of a control program, the operation mode control circuit comprising:

a control signal generator;

a write protection circuit for latching a second output signal from the control signal generator in response to a first output signal from the control signal generator and generating a write signal responsive to a logical value of the second output signal latched in the write protection circuit;

a first control circuit for latching a third output signal from the control signal generator in response to the write signal and for generating a first control signal responsive to the a logical value of the third output signal latched in the first control circuit;

a second control circuit for latching a fifth output signal from the control signal generator in response to a fourth output signal from the control signal generator, and for generating a second control signal responsive to a logical value of the fifth output signal latched in the second control circuit;

an OR gate for OR gating the first control signal and the second control signal and outputting an OR gate output as an operation mode setting signal,

wherein the write signal responsive to the logical value of the second output signal from the control signal generator is a signal with a fixed logical value if a logical value of the second output signal latched in the write protection circuit is “0”,

the write signal is a buffer signal that is a buffered version of the first output signal from the control signal generator if a logical value of the second output signal latched in the write protection circuit is “1”,

wherein the first control signal is supplied to a selection circuit that selects one signal generator from among a plurality of signal generators, each containing at least a data register, for sending a signal to the outside, and

wherein the operation mode setting signal is supplied to a circuit, which controls signal inputting from and signal outputting to the outside, to set the operation mode of the circuit.

5. An operation mode control circuit in a microcomputer for performing processes under a control of a control program, the operation mode control circuit comprising:

a control signal generator;

a write protection circuit for latching a second output signal from the control signal generator in response to a first output signal from the control signal generator, and for generating a write signal responsive to a logical value of the second output signal latched in the write protection circuit; and

a control circuit for latching a third output signal from the control signal generator in response to the write signal and for generating a control signal responsive to a logical value of the third output signal latched in the control circuit,

wherein the write signal is a signal with a fixed logical value if the logical value of the second output signal latched in the write protection circuit is “0”,

the write signal is a buffer signal that is the buffered version of the first output signal from the control signal generator if a logical value of the second output signal latched in the write protection circuit is “1”, and the control signal is supplied to a selection circuit that selects one signal generator from among a plurality of signal generators, each containing at least a data register, for sending a signal to the outside,

wherein the write protection circuit comprises:

buffer units for outputting one of the buffer signal resulting from the first output signal and the signal having the fixed logical value in response to the first output signal from the control signal generator, and

latch units for latching the second output signal from the control signal generator in response to the buffer signal and outputting a logical signal responsive to the logical value of the second output signal,

wherein the buffer units receives the logical signal from the latch units, and outputs a signal with the logical value thereof fixed in response to one logical value of the logical signal while outputting the buffer signal in response to the other logical value of the logical signal.

6. An operation mode control circuit in a microcomputer for performing processes under a control of a control program, the operation mode control circuit comprising

a control signal generator;

a write protection circuit for latching a second output signal from the control signal generator in response to a first output signal from the control signal generator, and for generating a write signal responsive to a logical value of the second output signal latched in the write protection circuit; and

a control circuit for latching a third output signal from the control signal generator in response to the write signal and for generating a control signal responsive to a logical value of the third output signal latched in the control circuit,

wherein the write signal is a signal with a fixed logical value if the logical value of the second output signal latched in the write protection circuit is “0”, the write signal is a buffer signal that is the buffered version of the first output signal from the control signal generator if a logical value of the second output signal latched in the write protection circuit is “1”, and the control signal is supplied to a selection circuit that selects one signal generator from among a plurality of signal generators, each containing at least a data register, for sending a signal to the outside,

wherein the write protection circuit comprises:

an AND gate for receiving, at one of input terminals thereof the first output signal from the control signal generator;

a buffer for outputting a buffer signal that is an logically inverted version of the second output signal from the control signal generator; and

a latch for receiving the buffer signal at a data terminal thereof, for latching the buffer signal in response to an output from the AND gate, and for generating a logical signal responsive to the logical value of the buffer signal, wherein the AND gate AND gates the logical signal and the first output signal.

7. A microcomputer comprising:

an operation mode control circuit including

a control signal generator,

a write protection circuit for latching a second output signal from the control signal generator in response to a first output signal from the control signal generator and generating a write signal responsive to the logical value of the second signal latched by the write protection circuit, the write signal being a signal with a fixed logical value if a logical value of the second output signal latched in the write protection circuit is “0”, the write signal being a buffer signal that is a buffered version of the first output signal if a logical value of the second output signal latched in the write protection circuit is “1”,

a first control circuit for latching a third output signal from the control signal generator in response to the write signal and for generating a first control signal responsive to the logical value of the latched third output signal,

a second control circuit for latching a fifth output signal from the control signal generator in response to a fourth output signal from the control signal generator, and for generating a second control signal responsive to the logical value of the latched fifth output signal, and

an OR gate for OR gating the first control signal and the second control signal and outputting an OR gate output as an operation mode setting signal;

a signal input and output control circuit for controlling of signal inputting from and signal outputting to the outside

a data register for latching a data signal from the operation mode control circuit in response to a data register write signal from the operation mode control circuit;

a timer for generating a clock with at least one constant period; and

a selection circuit for selecting one of the data register and the timer in response to the first control signal from the operation mode control circuit,

wherein the data register outputs a signal responsive to the data signal to the signal input and output control circuit.

Assignments (9)

Priority Claims (2)

Continuity (1)