Converter circuit for a limiter receiver structure and method for converting a signal in a limiter receiver structure
The present invention relates generally to a converter circuit with a limiter to convert an analog reception signal into a value-discrete limiter signal. An evaluation circuit determines a zero crossing distance signal from the temporal distances between successive zero crossings of the limiter signal. A synthesis circuit calculates a digital processing signal whose zero crossings correspond to those of the limiter signal and whose pulse shape has a smaller spectral width than a rectangular pulse.
1. A converter circuit for processing an analog reception signal for a limiter receiver structure, comprising:
a limiter configured to convert the analog reception signal into a time-continuous, value-discrete limiter signal characterized by a sequence of rectangular pulses;
an evaluation circuit coupled to the limiter, wherein the evaluation circuit detects the temporal distances between two successive zero crossings of the limiter signal and outputs a zero crossing distance signal in response to the detection of the temporal distances; and
a signal synthesis circuit receiving the zero crossing distance signal and generating a value- and time-discrete processing signal, wherein the zero crossings of the processing signal correspond to the zero crossings of the limiter signal and the pulse shape used for the signal synthesis has a smaller spectral width than a rectangular pulse of corresponding width.
2. The converter circuit of claim 1 , wherein the signal synthesis circuit uses a triangular shaped pulse.
3. The converter circuit of claim 1 , wherein the evaluation circuit detects the temporal distances between each of two successive zero crossings of the limiter signal with a time accuracy, and wherein the processing signal has a sampling rate that is less than a clock frequency.
4. The converter circuit of claim 3 , wherein the evaluation circuit comprises a zero crossing detector coupled to a counter.
5. The converter circuit of claim 1 , wherein the signal synthesis circuit has an interpolator that synthesizes the processing signal at support points determined by the sampling rate using the predetermined pulse shape.
6. The converter circuit of claim 1 , wherein the evaluation circuit detects the temporal distances between two successive zero crossings of the limiter signal with a time accuracy, and wherein the processing signal has a sampling rate that is less than a clock frequency.
7. The converter circuit of claim 6 , wherein the evaluation circuit comprises a zero crossing detector coupled to a counter.
8. A method for converting an analog reception signal in a limiter receiver structure, the method comprising:
generating a limited, time-continuous, value-discrete limiter signal characterized by a sequence of rectangular pulses from an analog reception signal;
determining the temporal distances between two successive zero crossings of the limiter signal; and
synthesizing a value- and time-discrete processing signal based on the temporal distances determined between successive zero crossings of the limiter signal, wherein the zero crossings of the processing signal correspond to the zero crossings of the limiter signal and the pulse shape used for the signal synthesis has a smaller spectral width than a rectangular pulse of corresponding width.
9. The method of claim 8 , wherein a triangular pulse is used as pulse shape.
10. The method of claim 8 , wherein the temporal distances between two successive zero crossings of the limiter signal are determined with a time accuracy and the processing signal is synthesized with a sampling rate that is less than a clock frequency.
11. The method of claim 10 , wherein the temporal distance between two successive zero crossings of the limiter signal are detected.
12. The method of claim 8 , wherein the value-and time-discrete processing signal is calculated in a manner dependent on the temporal distances between two zero crossings by an interpolation of the predetermined pulse shape at the support points determined by the sampling rate.
13. A converter circuit for processing an analog reception signal for a limiter receiver structure, comprising:
a limiter configured to convert the analog reception signal into a time-continuous, value-discrete limiter signal characterized by a sequence of rectangular pulses;
an evaluation circuit coupled to the limiter, wherein the evaluation circuit detects the temporal distances between two successive zero crossings of the limiter signal and outputs a zero crossing distance signal in response to the detection of the temporal distances; and
a signal synthesis circuit receiving the zero crossing distance signal and generating a value- and time-discrete processing signal, wherein the zero crossings of the processing signal correspond to the zero crossings of the limiter signal and the pulse shape used for the signal synthesis has a smaller spectral width than a triangular pulse of corresponding width.
14. The converter circuit of claim 13 , wherein the signal synthesis circuit has an interpolator that synthesizes the processing signal at support points determined by the sampling rate using the predetermined pulse shape.