IP Library Granted Patent US 7,542,728
Granted Patent B2
US 7,542,728 · App. 11/638,629 · Granted Jun 2, 2009

Dual-function wireless data terminal

Assignee: Altair Semiconductor Ltd.
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Quick Facts
Patent No.
US 7,542,728
App. No.
11/638,629
Granted
Jun 2, 2009
Kind
B2
Abstract

Apparatus for communication includes at least one RF receiver circuit, which is coupled to receive and downconvert first and second RF signals that are transmitted respectively over different, first and second wireless networks in accordance with different, first and second network protocols, so as to output first and second downconverted signals. A baseband processing circuit includes processing components that are coupled to receive and process the first and second downconverted signals so as to extract first and second data from the signals. The processing components have a first configuration for demodulating the first downconverted signals in accordance with the first network protocol and a second configuration for demodulating the second downconverted signals in accordance with the second network protocol.

Claims (27)

1. Apparatus for communication, comprising:

at least one radio frequency (RF) receiver circuit, which is coupled to receive first and second RF signals that are transmitted respectively over short-range and long-range wireless networks and carry first and second data modulated in accordance with respective network protocols, and which is arranged to downconvert the first and second RF signals so as to output first and second downconverted signals; and

a baseband processing circuit, comprising processing components that are coupled to receive and process the first and second downconverted signals so as to extract the first and second data from the signals, the processing components having a first configuration for demodulating the first downconverted signals received from the short-range network and a second configuration for demodulating the second downconverted signals received from the long-range network,

wherein the processing components comprise at least one programmable component, and wherein the baseband processing circuit comprises a memory for holding program code to drive the at least one programmable component, the program code comprising first code for driving the at least one programmable component in the first configuration and second code for driving the at least one programmable component in the second configuration.

2. The apparatus according to claim 1 , wherein the short-range wireless network is a wireless local area network (WLAN), and the long-range wireless network is a long-range wireless data network.

3. The apparatus according to claim 2 , wherein the long-range wireless data network is a WiMAX network.

4. The apparatus according to claim 1 , wherein the baseband processing circuit comprises a memory for holding both the first and the second data simultaneously.

5. The apparatus according to claim 4 , wherein the first and second data respectively comprise first and second data frames, and wherein the baseband processing circuit is arranged to tag the first and second data frames in the memory with different, respective first and second identifying tags.

6. The apparatus according to claim 1 , wherein the short-range and long-range networks use first and second medium access control (MAC) protocols, respectively, and wherein the at least one programmable component comprises a MAC controller, which is driven by the program code to operate in accordance with either of the first and second MAC protocols.

7. The apparatus according to claim 6 , wherein the MAC controller is driven by the first code in the first configuration to scan for a second connection to the second wireless network while receiving the first data over a first connection to the first wireless network, and after finding the second connection, to receive the second data over the second connection in the second configuration while maintaining the first connection at a reduced level of functionality relative to the first configuration.

8. The apparatus according to claim 7 , wherein the baseband processing circuit is arranged to unload the first code and load the second code into the memory upon finding the second connection, and to unload the second code and load the first code into the memory when the second connection is lost and the baseband processing circuit resumes the first configuration.

9. The apparatus according to claim 1 , wherein the baseband processing circuit is arranged, while receiving the first data over a first connection to the first wireless network in the first configuration, to scan for a second connection to the second wireless network, and upon finding the second connection, to begin receiving the second data over the second connection in the second configuration.

10. The apparatus according to claim 9 , wherein the baseband processing circuit is arranged, while receiving the second data over the second connection in the second configuration, to maintain the first connection at a reduced level of functionality relative to the first configuration and to return to the first configuration when the second connection is lost.

11. A method for communication, comprising:

receiving first and second radio frequency (RE) signals that are transmitted respectively over short-range and long-range wireless networks and carry first and second data modulated in accordance with respective network protocols;

downconverting the first and second RE signals so as to generate first and second downconverted signals; and

processing the first and second downconverted signals so as to extract the first and second data from the signals using a baseband processing circuit, which comprises processing components having a first configuration for demodulating the first downconverted signals received from the short-range network and a second configuration for demodulating the second downconverted signals received from the long-range network,

wherein the processing components comprise at least one programmable component, and wherein the baseband processing circuit comprises a memory for holding program code to drive the at least one programmable component, the program code comprising first code for driving the at least one programmable component in the first configuration and second code for driving the at least one programmable component in the second configuration.

12. The method according to claim 11 , wherein the short-range wireless network is a wireless local area network (WLAN), and the long-range wireless network is a long-range wireless data network.

13. The method according to claim 12 , wherein the long-range wireless data network is a WiMAX network.

14. The method according to claim 11 , wherein the baseband processing circuit comprises a memory for holding both the first and the second data simultaneously.

15. The method according to claim 14 , wherein the first and second data respectively comprise first and second data frames, and wherein processing the first and second downconverted signals comprises tagging the first and second data frames in the memory with different, respective first and second identifying tags.

16. The method according to claim 11 , wherein the short-range and long-range networks use first and second medium access control (MAC) protocols, respectively, and wherein the at least one programmable component comprises a MAC controller, which is driven by the program code to operate in accordance with either of the first and second MAC protocols.

17. The method according to claim 16 , wherein processing the first and second downconverted signals comprises driving the MAC controller using the first code in the first configuration to scan for a second connection to the second wireless network while receiving the first data over a first connection to the first wireless network, and after finding the second connection, to receive the second data over the second connection in the second configuration while maintaining the first connection at a reduced level of functionality relative to the first configuration.

18. The method according to claim 17 , wherein driving the MAC controller comprises unloading the first code and loading the second code into the memory upon finding the second connection, and unloading the second code and loading the first code into the memory when the second connection is lost and the baseband processing circuit resumes the first configuration.

19. The method according to claim 11 , wherein processing the first and second downconverted signals comprises scanning for a second connection to the second wireless network while receiving the first data over a first connection to the first wireless network in the first configuration, and upon finding the second connection, receiving the second data over the second connection in the second configuration.

20. The method according to claim 19 , wherein processing the first and second downconverted signals comprises maintaining the first connection at a reduced level of functionality relative to the first configuration while receiving the second data over the second connection in the second configuration, and returning to the first configuration when the second connection is lost.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2026
From: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
To: ALTAIR SEMICONDUCTOR LTD
Reel/Frame 075350/0600 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2023
From: SONY SEMICONDUCTOR ISRAEL LTD.
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 063225/0200 →
CHANGE OF NAME Recorded Apr 12, 2021
From: ALTAIR SEMICONDUCTOR LTD.
To: SONY SEMICONDUCTOR ISRAEL LTD.
Reel/Frame 055984/0171 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2013
From: ETV CAPITAL S.A.
To: ALTAIR SEMICONDUCTOR LTD.
Reel/Frame 031379/0389 →
SECURITY AGREEMENT Recorded Oct 3, 2013
From: ALTAIR SEMICONDUCTOR LTD
To: SILICON VALLEY BANK
Reel/Frame 031343/0670 →
SECURITY AGREEMENT Recorded Mar 11, 2010
From: ALTAIR SEMICONDUCTOR LTD.
To: ETV CAPITAL S.A.
Reel/Frame 024065/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2006
From: BITRAN, YIGAL; SOLOMON, EITAN
To: ALTAIR SEMICONDUCTOR LTD.
Reel/Frame 018687/0944 →
Continuity (2)
Provisional Application 6077216700 · Feb 9, 2006
Related Publication 20070184798A1 · Aug 9, 2007