Crossbar switch architecture for multi-processor SoC platform
View Patent ↗Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
1. A crossbar switch architecture comprising:
2×1 multiplexers connected in at least a 2×2 matrix form consisting of rows and columns,
wherein the 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, the other input line connected with an input/output line of a column including the corresponding multiplexer wherein the input/output line of the column including the corresponding multiplexer is connected to an input of each 2×1 multiplexer of the column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row,
wherein input/output lines of the rows are respectively connected with output lines of one slave-group multiplexer, and input lines of the slave-group multiplexer are respectively connected with slaves.
2. The crossbar switch architecture of claim 1 , wherein input/output lines of the rows are respectively connected with slaves, and input/output lines of the columns are respectively connected with masters.
3. The crossbar switch architecture of claim 2 , wherein the masters are processing units, and the slaves are peripheral interfaces.
4. The crossbar switch architecture of claim 1 , further comprising a switching controller for determining a connection path of each of the 2×1 multiplexers according to interpretation of an input command.
5. The crossbar switch architecture of claim 1 , wherein input/output lines of the rows are connected with each output line of at least two slave-group multiplexers, and input lines of the slave-group multiplexers are respectively connected with slaves.
6. The crossbar switch architecture of claim 5 , wherein the slave-group multiplexers comprise a plurality of 22 multiplexers having input lines connected with two of the input/output lines of the rows and output lines connected with two of the slaves.
7. The crossbar switch architecture of claim 1 , wherein input/output lines of the columns are respectively connected with output lines of one master-group multiplexer, and input lines of the master-group multiplexer are respectively connected with masters.
8. The crossbar switch architecture of claim 1 , wherein input/output lines of the columns are connected with each output line of at least two master-group multiplexers, and input lines of the master-group multiplexers are respectively connected with masters.
9. The crossbar switch architecture of claim 8 , wherein the master-group multiplexers comprise a plurality of 2×2 multiplexers having input lines connected with two of the input/output lines of the columns and output lines connected with two of the masters.