IP Library Granted Patent US 7,586,432
Granted Patent B2
US 7,586,432 · App. 12/019,565 · Granted Sep 8, 2009

A/D converter

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,586,432
App. No.
12/019,565
Granted
Sep 8, 2009
Kind
B2
Abstract

An A/D converter compares one or more analog voltages to be converted with a reference voltage given by a voltage change value of ramp voltage whose voltage value changes monotonically for a certain period or a voltage proportional to the voltage change value, converts each analog voltage to a digital value corresponding to the reference voltage, and outputs it, the A/D converter comprising an arithmetic unit for comparison between the analog voltage and reference voltage with respect to each analog voltage, the arithmetic unit having a first power supply line for receiving a power supply voltage, wherein the first power supply line is provided as another power supply line not affected by voltage fluctuation of a second power supply line for supplying a system power supply voltage by providing a MOS transistor whose gate terminal is connected to a stabilized voltage source between the first and second power supply lines.

Claims (30)

1. An A/D converter for sampling and holding one or more analog voltages to be converted, comparing the sampled and held one or more analog voltages to be converted with a reference voltage given by a voltage change value of a ramp voltage having a voltage value changing monotonically for a certain period or a voltage proportional to the voltage change value, converting each of the one or more analog voltages to be converted to a digital value corresponding to the reference voltage, and outputting it, wherein

an arithmetic unit that compares each of the one or more analog voltages to be converted with the reference voltage is provided with respect to each of the analog voltages to be converted,

each arithmetic unit provided with respect to each of the analog voltages to be converted including a first power supply line for receiving a power supply voltage individually, and

each first power supply line being provided as another power supply line not affected by a voltage fluctuation of a second power supply line for supplying a power supply voltage to circuits other than each arithmetic unit provided with respect to each of the analog voltages to be converted.

2. The A/D converter according to claim 1 , further comprising:

an N channel-type MOSFET having a source terminal and a drain terminal connected to the first power supply line and the second power supply line, respectively; and

a first stabilized voltage source for outputting a stabilized voltage not affected by the voltage fluctuation of the second power supply line, to a gate terminal of the N channel-type MOSFET.

3. The A/D converter according to claim 1 , wherein

a first ground voltage line for supplying a ground voltage to each arithmetic unit provided with respect to each of the analog voltages to be converted is provided as another ground voltage line not affected by a voltage fluctuation of a second ground voltage line for supplying a ground voltage to circuits other than each arithmetic unit provided with respect to each of the analog voltages to be converted.

4. The A/D converter according to claim 3 , further comprising:

a P channel-type MOSFET having a source terminal and a drain terminal connected to the first ground voltage line and the second ground voltage line, respectively; and

a second stabilized voltage source for outputting a stabilized voltage not affected by the voltage fluctuation of the second ground voltage line, to a gate terminal of the P channel-type MOSFET.

5. The MD converter according to claim 2 , wherein

a plurality of analog voltages are converted by a plurality of arithmetic units, with each arithmetic unit of the plurality of arithmetic units respectively converting a corresponding one of the plurality of analog voltages,

a plurality of gate terminals of a plurality of N channel-type MOSFETs that are each connected to respective corresponding ones of first power supply lines of the plurality of arithmetic units are connected to each other, and

an output voltage of the first stabilized voltage source is outputted to each of the plurality of gate terminals of the plurality of N channel-type MOSFETs.

6. The A/D converter according to claim 4 , wherein

a plurality of analog voltages are converted by a plurality of arithmetic units, with each arithmetic unit of the plurality of arithmetic units respectively converting a corresponding one of the plurality of analog voltages,

a plurality of gate terminals of a plurality of P channel-type MOSFETs that are each connected to respective corresponding ones of first ground voltage lines of the plurality of arithmetic units are connected to each other, and

an output voltage of the second stabilized voltage source is outputted to each of the plurality of gate terminals of the plurality of P channel-type MOSFETs.

7. The A/D converter according to claim 1 , further comprising:

a ramp voltage generator unit for generating the ramp voltage;

a counter for counting a digital value corresponding to the reference voltage and outputting it;

a voltage comparison circuit for sampling and holding the analog voltage to be converted and comparing the reference voltage with the analog voltage to be converted by each arithmetic unit provided with respect to each of the analog voltages to be converted, and changing an output when the reference voltage equals the analog voltage to be converted; and

a latch circuit for latching the digital value outputted from the counter when the output of the voltage comparison circuit is changed, and outputting the latched digital value.

8. The A/D converter according to claim 1 , wherein

each arithmetic unit provided with respect to each of the analog voltages to be converted comprises an inverter circuit, the A/D converter further comprising

a voltage synthesis circuit for generating a composite voltage provided by adding a differential voltage between the analog voltage to be converted and the reference voltage, to an input determination voltage of the inverter circuit, as an input voltage of the inverter circuit.

9. The A/D converter according to claim 1 , wherein

each arithmetic unit provided with respect to each of the analog voltages to be converted comprises a differential input type operation amplifier receiving the analog voltage to be converted and the ramp voltage as input voltages.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2024
From: SHARP KABUSHIKI KAISHA
To: RS TECHNOLOGIES CO., LTD.
Reel/Frame 066491/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2008
From: MARUYAMA, MASAHIKO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 020903/0080 →
Priority Claims (1)
JP 2007-014917 · Jan 25, 2007 · national
Continuity (1)
Related Publication 20080198049A1 · Aug 21, 2008