IP Library Granted Patent US 7,586,608
Granted Patent B1
US 7,586,608 · App. 11/729,814 · Granted Sep 8, 2009

Wafer-level testing of optical and optoelectronic chips

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Quick Facts
Patent No.
US 7,586,608
App. No.
11/729,814
Granted
Sep 8, 2009
Kind
B1
Abstract

This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.

Claims (34)

1. A method, comprising:

directing a probe beam from an optical probe located above a surface of a wafer to the surface of the wafer;

using an optical alignment structure on the wafer to direct a portion of the probe beam along a direction above the wafer;

using the portion of the probe beam from the optical alignment structure as a guide to adjust a position of the optical probe relative to the optical alignment structure;

using the optical alignment structure as a guide to move the wafer to place the optical probe at a first location above the wafer;

using a positional relationship between the first location and a selected location on the wafer to move the wafer to position the optical probe from the first location to the selected location above the wafer; and

using the optical probe to conduct an optical test on a component located at the selected location and eliminating the component from a subsequent processing step if the component fails a pre-determined test criteria of the optical test,

wherein the optical alignment structure comprises an optical diffraction grating structure,

wherein the optical diffraction grating structure provides a reflective surface for the incident probe beam.

2. The method of claim 1 , further comprising a method for creating the optical diffraction grating structure with lithography, material deposition and etching, wherein the material is dielectric material, metal, silicon, or polysilicon.

3. A method, comprising:

directing a probe beam from an optical probe located above a surface of a wafer to the surface of the wafer;

using an optical alignment structure on the wafer to direct a portion of the probe beam along a direction above the wafer;

using the portion of the probe beam from the optical alignment structure as a guide to adjust a position of the optical probe relative to the optical alignment structure; and

using the optical probe to collect an optical output from the wafer to test an optical component at a wafer location and eliminating the optical component from a subsequent processing step if the optical component fails a pre-determined test criteria,

wherein the optical alignment structure comprises an optical diffraction grating structure,

wherein the optical diffraction grating structure provides a highly reflective surface for the incident probe beam.

4. A method, comprising:

directing a probe beam from an optical probe located above a surface of a wafer to the surface of the wafer;

using an optical alignment structure on the wafer to direct a portion of the probe beam along a direction above the wafer,

using the portion of the probe beam from the optical alignment structure as a guide to adjust a position of the optical probe relative to the optical alignment structure;

using a known spatial relationship between a position of each component on the wafer relative to the optical alignment structure to align the optical probe with at least one optical component on the wafer;

using the probe beam from the optical probe to optically test the at least one optical component; and

eliminating the at least one component from a subsequent processing step if the at least one optical component fails a pre-determined test criteria,

wherein the optical alignment structure comprises an optical diffraction grating structure,

wherein the optical diffraction grating structure provides a reflective surface for the incident probe beam.

5. The method as in claim 4 , further comprising measuring an electrical signal produced on the wafer due to an interaction between an optical component on the wafer and the probe beam.

6. The method as in claim 4 , further comprising collecting an output beam from the wafer by using an optical fiber above the wafer and using an optical detector to measure the output beam received by the fiber.

7. The method as in claim 4 , further comprising performing wafer-level testing on electronic components on the wafer.

8. The method as in claim 4 , further comprising performing wafer-level testing on optical components on the wafer.

9. The method as in claim 4 , further comprising performing wafer-level testing on optoelectronic components on the wafer.

10. The method as in claim 4 , wherein the optical probe comprises a fiber array of fibers, the method further comprising:

using one fiber in the fiber array to deliver the probe beam to the wafer; and

using another fiber in the fiber array to receive the portion of the probe beam from the optical alignment structure.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY AGREEMENT Recorded Mar 17, 2010
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 024091/0191 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2007
From: GUNN III, LAWRENCE C.; MALENDEVICH, ROMAN; PINGUET, THIERRY J.; RATTIER, MAXIME JEAN; SUSSMAN, MYLES; WITZENS, JEREMY
To: LUXTERA, INC.
Reel/Frame 019174/0659 →