Bipolar transistors with vertical structures
A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.
1. A method, comprising:
ion implanting a dopant into a semiconductor substrate to form a conductive area therein;
forming a sequence of semiconductor layers on the substrate, the sequence including a collector layer, a base layer in contact with the collector layer, and an emitter layer in contact with the base layer, one of the semiconductor layers having a bottom surface in contact with the conductive area;
etching away a portion of two of the semiconductor layers to expose a portion of the one of the semiconductor layers; and
ion implanting a dopant into a portion of the exposed portion of the one of the semiconductor layers to form a conductive channel between the conductive area and a top surface of the exposed portion of the one of the semiconductor layers.
2. The method of claim 1 , further comprising treating another portion of the one of the semiconductor layers to make the another portion nonconductive, the another portion laterally surrounding a device footprint region that includes the implanted portion of the one of the semiconductor layers.
3. The method of claim 1 , wherein the one of the semiconductor layers is the collector layer and the conductive area is a conducting subcollector connection.
4. The method of claim 1 , further comprising:
etching the last formed one of the semiconductor layers to define intrinsic and extrinsic regions of a vertical structure for a bipolar transistor.
5. The method of claim 4 , further comprising:
ion implanting a dopant into a portion of the base layer to form an implant doped base extension.
6. The method of claim 5 , wherein the ion implanting into a portion of the base layer produces in the base extension a concentration of dopant atoms that is at least two times as high as a concentration of dopant atoms in the portion of the base layer in the intrinsic region.
7. The method of claim 5 , wherein the base extension is thicker than a portion of the base layer in the intrinsic region.
8. The method of claim 1 , wherein the forming a sequence comprises performing a sequence of epitaxial growths of doped semiconductor layers.
9. The method of claim 5 , further comprising:
forming an electrode on a portion of the last formed one of the semiconductor layers; and
forming an electrode on the base extension; and
wherein the two electrodes are separated by a lateral gap.
10. The method of claim 1 , wherein each formed layer comprises one of InP, InGaP, InGaAs, InGaAsP, GaAs, InAlGaAs, AlGaAs, GaSb, AlSb, GaAlSb, InSb, InAsSb, GaAsSb, InGaSb, GaN, InN, AlN, InGaN, AlGaN, and InGaAlN.