Semiconductor flash device
View Patent ↗A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.
1. A floating gate transistor comprising:
a lower tunnel-oxide formed over a substrate;
an upper dielectric formed over said tunnel-oxide;
a control gate formed over said upper dielectric;
a semiconductor fin disposed directly on said substrate and wherein said lower tunnel-oxide is a layer that extends along said substrate and conterminously over sides and top of said semiconductor fin and a channel of said transistor is formed within said semiconductor fin; and
a p-n junction formed between said tunnel-oxide and said upper dielectric, wherein said p-n junction is a heterojunction formed between two layers of semiconductor material having different bandgaps.
2. The floating gate transistor as in claim 1 , wherein said p-n junction comprises a quantum well.
3. The floating gate transistor as in claim 1 , wherein said different bandgaps differ by at least 0.05 ev.
4. The floating gate transistor as in claim 1 , wherein said two layers of semiconductor material comprise a layer of SiGe and a layer of Si.
5. The floating gate transistor as in claim 1 , wherein said two layers of semiconductor material comprise a first layer formed of III-V material and a second layer formed of II-VI material.
6. The floating gate transistor as in claim 1 , wherein said two layers of semiconductor material comprise a layer of p-Si and a layer of n-SiGe.
7. The floating gate transistor as in claim 1 , wherein said lower tunnel-oxide includes a thickness of less than 90 angstroms and said upper dielectric includes a thickness of less than 90 angstroms.
8. The floating gate transistor as in claim 1 , wherein said floating gate transistor is erasable using a voltage no greater than 8 volts.
9. The floating gate transistor as in claim 1 , wherein said floating gate transistor is programmable using a voltage no greater than 8 volts.
10. The floating gate transistor as in claim 1 , wherein said floating gate transistor is an NMOS transistor and mobile carriers stored at said p-n junction comprise electrons.
11. The floating gate transistor as in claim 1 , wherein said floating gate transistor is an NMOS transistor and mobile carriers stored at said p-n junction comprise holes.
12. The floating gate transistor as in claim 1 , wherein said floating gate transistor comprises a PMOS transistor.
13. A floating gate transistor comprising:
a lower tunnel-oxide formed over a substrate;
an upper dielectric formed over said tunnel-oxide;
a control gate formed over said upper dielectric; and
a p-n junction formed between said tunnel-oxide and said upper dielectric, wherein said p-n junction is a heterojunction formed between two layers of semiconductor material having different bandgaps,
wherein said two layers of semiconductor material comprise a layer of n-Si and a layer of p-SiGe and said p-n junction comprises an electron quantum well.
14. A semiconductor flash memory device comprising:
a lower tunnel-oxide formed over a substrate;
an upper dielectric formed over said tunnel-oxide;
a control gate formed over said upper dielectric;
a quantum well formed at a p-n junction disposed between said tunnel-oxide and said upper dielectric;
a semiconductor fin disposed directly on said substrate and wherein said lower tunnel-oxide is a layer that extends along said substrate and conterminously over sides and top of said semiconductor fin, wherein a channel of a transistor is formed within said semiconductor fin; and
charge stored in said quantum well, wherein said p-n junction is a heterojunction formed between two layers of semiconductor material, said two layers of semiconductor material comprising an n-type layer adjacent a p-type layer and including respective bandgaps that differ by at least 0.05 eV.
15. A floating gate transistor comprising:
a lower tunnel-oxide formed over a substrate;
an upper dielectric formed over said tunnel-oxide;
a control gate formed over said upper dielectric; and
a p-n junction and a further p-n junction formed between said tunnel-oxide and said upper dielectric,
wherein each of said p-n junction and said further p-n junction is a heterojunction formed between two layers of semiconductor material having different bandgaps, said p-n junction and said further p-n junction created by three layers formed between said lower tunnel-oxide and said upper dielectric, said three layers including a middle semiconductor layer with a first bandgap interposed between an upper semiconductor layer and a lower semiconductor layer each formed of a material having a different bandgap than said middle semiconductor layer.