IP Library Granted Patent US 7,608,479
Granted Patent B2
US 7,608,479 · App. 11/332,262 · Granted Oct 27, 2009

Method of manufacturing semiconductor device and method of treating electrical connection section

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,608,479
App. No.
11/332,262
Granted
Oct 27, 2009
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.

Claims (26)

1. A method of manufacturing a semiconductor device, comprising:

providing an electrical connection section and a protective film, the electrical connection section being electrically connected with a semiconductor substrate, a first part of the protective film covering at least a first area of a first surface of the electrical connection section, the first part of the protective film having a first face facing the first area of the first surface of the electrical connection section and a second face opposite to the first face, the protective film having an opening disposed on a second area of the first surface of the electrical connection section;

applying a paste containing acid on the second area of the first surface of the electrical connection section and the second face of the first part of the protective film after providing of the electrical connection section and the protective film;

removing the paste from the second area of the first surface of the electrical connection section by washing the electrical connection section;

providing a solder to the electrical connection section through a flux after the removing of the paste; and

providing the solder in such a manner that the solder is in touch with the second area of the first surface of the electrical connection section after the providing of the solder to the electrical connection section.

2. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the paste applied in the applying of the paste includes a material that is the same as a material for the flux provided in the providing of the solder to the electrical connection section.

3. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the paste applied in the applying of the paste includes a material containing an acid at a ratio higher than that of a material for the flux provided in the providing of the solder to the electrical connection section.

4. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the paste applied in the applying of the paste includes a material containing an acid having a higher reducing power than that of an acid contained in the flux provided in the providing of the solder to the electrical connection section.

5. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the applying of the paste and the removing of the paste are performed in air or in an oxygen atmosphere.

6. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the acid contained in the paste is an organic acid.

7. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the acid contained in the paste is an inorganic acid.

8. The method of manufacturing a semiconductor device as defined in claim 1 ,

wherein the semiconductor substrate is mounted on an interposer; and

wherein the electrical connection section is a land formed on the interposer.

9. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the electrical connection section is an electrode pad formed on the semiconductor substrate.

10. The method of manufacturing a semiconductor device as defined in claim 1 ,

wherein a resin layer is formed on the semiconductor substrate; and

wherein the electrical connection section is a land formed on the resin layer.

11. The method of manufacturing a semiconductor device as defined in claim 1 ,

wherein multiple electrical connection sections are arranged in rows and columns; and

wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned on an outer end of the rows and columns.

12. The method of manufacturing a semiconductor device as defined in claim 11 , wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned at outer corners of the rows and columns.

13. The method of manufacturing a semiconductor device as defined in claim 11 ,

wherein the electrical connection sections are arranged in rows and columns in an area enclosing a specific area; and

wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned on an inner end of the rows and columns closest to the specific area.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2020
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 053671/0900 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2006
From: NAKAYAMA, HIROHISA; SATO, SHIRO; SHOJI, MASANOBU; NOSAKA, HITOSHI
To: SEIKO EPSON CORPORATION
Reel/Frame 017475/0088 →
Priority Claims (1)
JP 2005-011763 · Jan 19, 2005 · national
Continuity (1)
Related Publication 20060160347A1 · Jul 20, 2006