IP Library Granted Patent US 7,626,532
Granted Patent B2
US 7,626,532 · App. 12/020,425 · Granted Dec 1, 2009

A/D converter

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,626,532
App. No.
12/020,425
Granted
Dec 1, 2009
Kind
B2
Abstract

An A/D converter comprises a ramp voltage generation circuit, a voltage comparison circuit comprising an arithmetic unit comparing an analog voltage to be converted with a reference voltage showing the voltage change of a ramp voltage, and changing an output when the reference voltage equals the analog voltage, a counter counting and outputting a digital value corresponding to the reference voltage, a latch circuit latching and outputting the digital value when the output of the voltage comparison circuit changes, an averaging process circuit to obtain an average noise voltage, a target noise voltage setting circuit setting a target noise voltage, and a control circuit adjusting at least one of a counting start timing of the counter with respect to a control reference timing, or the criterion level of the reference voltage at the counting start timing, based on a difference between the average noise voltage and the target noise voltage.

Claims (31)

1. An A/D converter comprising:

a ramp voltage generation circuit generating a ramp voltage having a voltage value changing monotonically for a certain period;

a voltage comparison circuit comprising an arithmetic unit sampling and holding an analog voltage to be converted and comparing the sampled and held analog voltage to be converted, with a reference voltage given by a voltage change value of the ramp voltage generated from the ramp voltage generation circuit or a voltage value proportional to the voltage change value, and changing an output when the reference voltage equals the analog voltage to be converted;

a counter counting a digital value corresponding to the reference voltage and outputting the digital value;

a latch circuit latching the digital value outputted from the counter when the output of the voltage comparison circuit is changed and outputting the digital value;

an averaging process circuit averaging a noise component contained in the analog voltage to be converted to obtain an average noise voltage;

a target noise voltage setting circuit setting a target noise voltage as a target value of the average noise voltage; and

a control circuit performing at least one adjustment of a counting start timing of the counter with respect to a control reference timing at which the reference voltage starts to change from a criterion level by the ramp voltage generation circuit, or adjustment of the criterion level of the reference voltage at the counting start timing of the counter, based on a difference between the average noise voltage and the target noise voltage.

2. The A/D converter according to claim 1 , wherein

the control circuit calculates an index value showing the difference between the average noise voltage and the target noise voltage, and a counter standby time to adjust the counting start timing of the counter in accordance with the index value, and adjusts the counting start timing of the counter in accordance with the counter standby time.

3. The A/D converter according to claim 1 , wherein

the control circuit calculates an index value showing the difference between the average noise voltage and the target noise voltage, and a counter standby time to adjust the counting start timing of the counter in accordance with the index value, and delays the counting start timing with respect to the control reference timing in accordance with the counter standby time when the average noise voltage is above the target noise voltage, or hastens the counting start timing with respect to the control reference timing in accordance with the counter standby time when the average noise voltage is below the target noise voltage, and further calculates an adjustment amount of the criterion level of the reference voltage at the control reference timing based on the index value and changes the criterion level of the reference voltage by the adjustment amount in a direction opposite to a voltage change direction of the ramp voltage before the control reference timing.

4. The A/D converter according to claim 1 , wherein

the control circuit calculates an index value showing the difference between the average noise voltage and the target noise voltage, and an adjustment amount of the criterion level of the reference voltage at the counting start timing based on the index value, and changes the criterion level of the reference voltage based on the adjustment amount in a voltage change direction of the ramp voltage before the counting start timing.

5. The A/D converter according to claim 4 , wherein

when the average noise voltage is below the target noise voltage, the control circuit calculates an adjustment amount of the criterion level of the reference voltage at the counting start timing based on the index value, and changes the criterion level of the reference voltage based on the adjustment amount in a direction opposite to a voltage change direction of the ramp voltage before the counting start timing.

6. The A/D converter according to claim 1 , wherein

the ramp voltage generation circuit comprises a first current mirror circuit and a second current mirror circuit that duplicate a current value from a constant current source, an integral capacity charged by a current duplicated by the first current mirror circuit and discharged by a current duplicated by the second current mirror circuit, and a switch circuit alternatively switching between charging the integral capacity by the first current mirror circuit and discharging the integral capacity by the second current mirror circuit.

7. The A/D converter according to claim 1 , wherein

the arithmetic unit comprises an inverter circuit, and

a voltage synthetic circuit generating a composite voltage as an input voltage of the inverter circuit, the composite voltage provided by adding a difference voltage between the analog voltage to be converted and the reference voltage, to an input determination voltage of the inverter circuit.

8. The A/D converter according to claim 1 , wherein

the arithmetic unit comprises a differential input type of operation amplifier receiving the analog voltage to be converted and the ramp voltage as input voltages.

9. The A/D converter according to claim 1 , wherein

the control circuit inversely operates the ramp voltage generation circuit when the criterion level of the reference voltage is changed in a direction opposite to a voltage change direction of the ramp voltage.

10. A sensor system comprising:

a sensor having a plurality of photoelectric conversion elements arranged in a matrix;

a plurality of A/D conversion units each provided in each column of the sensor, the A/D conversion units comprising the voltage comparison circuit and the latch circuit of the A/D converter according to claim 1 ;

the ramp voltage generation circuit, the counter, the averaging process circuit, the target noise voltage setting circuit, and the control circuit, of the A/D converter, wherein

an optical black pixel part shielded from light is provided at a part of marginal portions of the sensor, and

the averaging process circuit averages A/D converted values of the A/D conversion unit from an output signal of the optical black pixel part to get the average noise voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2024
From: SHARP KABUSHIKI KAISHA
To: RS TECHNOLOGIES CO., LTD.
Reel/Frame 066491/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2008
From: MARUYAMA, MASAHIKO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 020857/0174 →
Priority Claims (1)
JP 2007-018771 · Jan 30, 2007 · national
Continuity (1)
Related Publication 20090021411A1 · Jan 22, 2009