Ge short wavelength infrared imager
A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
1. A method for fabricating a germanium (Ge) short wavelength infrared (SWIR) imager, the method comprising:
providing a silicon (Si) substrate with doped wells;
forming a relaxed Ge-containing film with threading dislocations at a Ge/Si interface;
doping the Ge/Si interface, forming a doped Ge-containing buffer layer;
forming an array of pin diodes with flip-chip interfaces in the Ge-containing film;
forming an array of Si CMOS readout circuits, each readout circuit having a zero volt diode bias interface; and,
flip-chip bonding the array of pin diode interfaces to the array of readout circuit interfaces.
2. The method of claim 1 wherein forming the array of pin diodes includes forming the diode arrays with active regions sufficiently thick to absorb incident light.
3. The method of claim 2 wherein forming the diode arrays with active regions sufficiently thick to absorb incident light includes forming a thickness sufficient to absorb light having a wavelength in the range of about 1100 nm to 1600 nm.
4. The method of claim 3 wherein forming the diode arrays with active regions sufficiently thick to absorb incident light includes forming an active region with a thickness in the range of about 1 to 5 microns.
5. The method of claim 1 wherein forming the array of Si CMOS readout circuits includes forming readout circuits having a diode interface with a bias of less than 0.001 volts.
6. The method of claim 1 wherein forming the array of pin diodes includes:
after forming the relaxed Ge-containing buffer layer, forming doped guard rings in the relaxed Ge-containing film down to the level of the doped Ge-containing buffer layer, creating an array of isolated Ge intrinsic regions;
selectively doping surface regions of each Ge intrinsic region, forming doped surface regions;
covering the Ge-containing film with an ILD; and,
forming flip-chip contacts through the ILD to the doped surface regions.
7. The method of claim 1 wherein forming the relaxed Ge-containing film includes:
using a chemical vapor deposition (CVD) process, depositing a first layer of Ge-containing film at a temperature in a range of about 250 to 300° C.;
CVD depositing a second layer of Ge-containing film, overlying the first layer, at a temperature in a range of about 600 to 700° C.;
covering the Ge-containing film with a silicon nitride layer; and,
cyclically annealing.