Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock signals are applied in parallel
View Patent ↗A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF 1 , FF 2 ) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.
1. A memory system comprising a memory controller and at least one memory board, the memory board comprising a digital data buffer having at least one data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, the buffer further having a clock output for providing an output clock signal to the data destination device and a phase-locked loop with a clock input, a feedback input, a feedback output and a plurality of clock outputs; wherein: the data path has a first data register with a data input, a clock input and a data output; the data path has a second data register with a data input, a clock input and a data output; the data input of the buffer is connected to the data input of the first data register; the data output of the first data register is connected to the data input of the second data register; the data output of the buffer is connected to the data output of the second data register; the clock input of the buffer is connected to the clock input of the the first data register; the clock input of the buffer is connected to the clock input of the phase-locked loop; a first clock output of the phase-locked loop provides a feedback clock signal for application to the feedback input of the phase-locked loop; a second clock output of the phase-locked loop provides a clock signal shifted in phase by a fraction of the clock period with respect to the feedback clock signal for application to the clock input of the second data register; and a third clock output of the phase-locked loop provides a clock signal shifted in phase by an amount of 180 deg. plus a fraction of the clock period with respect to the feedback clock signal for application to the clock input of the data destination device.
2. The digital data buffer of claim 1 , wherein the fraction of the clock period is adjusted to optimize the propagation delay of data bits through the buffer as measured from an edge of the input clock signal to a corresponding edge of the output signal.
3. The digital data buffer of claim 1 , wherein the fraction of the clock period is set to zero.
4. The digital data buffer of claim 1 , wherein the fraction of the clock period is adjusted by applying a digital control word to the phase-locked loop.
5. The digital data buffer of claim 1 , wherein the data input, the clock input and the feedback input each have an input stage that converts a differential input to a single-ended output.
6. The digital data buffer of claim 5 , wherein the phase-locked loop has a feedback loop external to integrated circuitry of the phase-locked loop, the feedback input is matched with the clock input and the feedback output is matched with the clock output.
7. The digital data buffer of claim 6 , wherein the data output is matched with the clock output, the clock output and the feedback output each including a delay element introducing a delay corresponding to the propagation delay of the second data register.
8. The digital data buffer of claim 1 , wherein the data output, the clock output and the feedback output each have an output stage converting a single-ended input to a differential output.
9. The digital data buffer of claim 8 , wherein the phase-locked loop has a feedback loop external to integrated circuitry of the phase-locked loop, the feedback input is matched with the clock input and the feedback output is matched with the clock output.
10. The digital data buffer of claim 9 , wherein the data output is matched with the clock output, the clock output and the feedback output each including a delay element introducing a delay corresponding to the propagation delay of the second data register.
11. The digital data buffer of claim 1 , wherein the digital input signal is n bits wide and the buffer comprises n similar data paths each with a first data register clocked by the clock input signal and a second data register clocked by the clock signal from the second clock output of the phase-locked loop.
12. The digital data buffer of claim 1 , and comprising at least two of said data paths each with a first data register clocked by the clock input signal and a second data register, wherein the phase-locked loop has at least two clock outputs each providing a clock signal shifted in phase by a fraction of the clock period with reference to the feedback clock signal and the second data registers in said at least two data paths are clocked by different ones of said phase-shifted clock signals.
13. The digital data buffer according to claim 12 , wherein the third clock output of the phase-locked loop provides a clock signal shifted in phase by an amount of 180 deg. plus a fraction of the clock period with respect to the feedback clock signal, said fraction being different from the fractions by which the clock signals applied to the second data registers are phase-shifted.
14. The digital data buffer according to claim 12 , wherein the third clock output of the phase-locked loop provides a clock signal shifted in phase by an amount of 180 deg. plus a fraction of the clock period with respect to the feedback clock signal, said fraction being the same as one of the fractions by which the clock signals applied to the second data registers are phase-shifted.