Vertical-type non-volatile memory devices
In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
1. A semiconductor device comprising:
a substrate extending in a horizontal direction;
a plurality of interlayer dielectric layers on the substrate;
a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;
a vertical channel extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns;
a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel; and
a charge trapping layer between each corresponding gate pattern and gate insulating layer, the charge trapping layer including: a first portion extending in the vertical direction between the gate pattern and the gate insulating layer; a second portion extending in the horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer; and a third portion extending in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.
2. The semiconductor device of claim 1 wherein the substrate and the vertical channel comprise single-crystal semiconductor material.
3. The semiconductor device of claim 1 wherein the charge trapping layer comprises a floating gate comprising a conducting or a semi-conducting material.
4. The semiconductor device of claim 1 wherein the gate insulating layer comprises a thermal oxide layer.
5. The semiconductor device of claim 1 wherein:
an upper-most gate pattern of the plurality of gate patterns comprises an upper select gate of an upper select transistor;
a lower-most gate pattern of the plurality of gate patterns comprises a lower select gate of a lower select transistor;
remaining gate patterns of the plurality of gate patterns between the upper select gate and the lower select gate comprise control gates of memory cell transistors of a common string of the semiconductor device;
control gates of memory cell transistors sharing a same layer of the device arranged in a first horizontal direction of the semiconductor device are connected to provide word lines of the semiconductor device;
memory cell transistors of a common string of the semiconductor device are coupled together in series by the vertical channel;
upper portions of vertical channels arranged in a second horizontal direction of the semiconductor device are connected to provide bit lines of the semiconductor device; and
the semiconductor device comprises a non-volatile semiconductor memory device.
6. The semiconductor device of claim 1 wherein the plurality of interlayer dielectric layers each comprise a multiple-layered structure comprising a lower insulating layer, an intermediate insulating layer and an tipper insulating layer, the lower and upper insulating layers comprising a material that has etch selectivity relative to the intermediate insulating layer.