Dynamic power management in system on chips (SOC)
View Patent ↗A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.
1. A system on chip with efficient power management, comprising:
a plurality of processors, each processor being configured to selectively lock and unlock each of a plurality of global feasibility variables based on a power requirement of the processor, the plurality of global feasibility variables respectively corresponding to distinct power modes of the system on chip;
a plurality of peripherals, each peripheral being configured to selectively lock and unlock each of the plurality of global feasibility variables based on a power requirement of the peripheral;
a means for dynamically defining a feasibility of entering a low power mode of operation based at least in part on at least one of said processors or said peripherals locking or unlocking one or more of the global feasibility variables; and
a means for entering or exiting a low power state based on said defined feasibility.
2. A system on chip as claimed in claim 1 , wherein said locking/unlocking is done by incrementing/decrementing the feasibility variables.
3. A system on chip as claimed in claim 1 , wherein a global feasibility variable is maintained for each possible operating mode of the system on chip.
4. A system on chip as claimed in claim 1 , wherein a minimum frequency of operation in a specific operating mode is also defined based on an activity state of at least one of said processors.
5. A system on chip as claimed in claim 1 , further comprising a stalling machine attached to some of the peripherals for smooth transition to low power modes.
6. A system for dynamic power management in a system on chip, comprising:
a plurality of components, each component being configured to selectively lock and unlock each of a plurality of global feasibility locks based on a power requirement of the component, the plurality of global feasibility locks respectively corresponding to distinct power modes of the system on chip;
a means for dynamically defining a feasibility of entering a low power mode of operation based on at least some of the plurality of components locking or unlocking the feasibility locks, and
a means for entering or exiting from a low power mode based on said defined feasibility.
7. A system as claimed in claim 6 , wherein said locking/unlocking is done by incrementing/decrementing the feasibility variables locks.
8. A method for dynamic power management in a system on chip, said method comprising the steps of:
maintaining feasibility variables that respectively corresponding to different operating modes of the system on chip;
providing access to said feasibility variables for different system components of the system on chip to selectively lock or unlock said feasibility variables depending upon power requirements of the components; and
checking said feasibility variables and changing the operating mode of system on chip based on said feasibility variables.
9. A method for dynamic power management as claimed in claim 8 , wherein while locking a particular feasibility variable corresponding to a specific operating mode, the system components also locks a minimum frequency of that operating mode.
10. A method for dynamic power management as claimed in claim 8 , wherein said locking or unlocking is done by incrementing/decrementing the feasibility variables.
11. A method for dynamic power management in a system on chip, said method comprising the steps of:
maintaining feasibility variables that respectively correspond to different operating modes of the system on chip;
receiving indications from different components of the system to lock/unlock a particular one or more of the feasibility variables;
locking/unlocking the particular one or more feasibility variables based on said received indications of different system components; and
checking said feasibility variables and changing the operating mode of system on chip based on said feasibility variables.
12. A method for dynamic power management as claimed in claim 11 , wherein while locking a particular feasibility variable corresponding to a specific operating mode, the system components also locks a minimum frequency of that operating mode.
13. A method for dynamic power management as claimed in claim 11 , wherein said locking or unlocking is done by incrementing/decrementing the feasibility variables.
14. A system on chip with efficient power management, comprising:
a central processor core running a native operating system;
a hardware accelerator containing a digital signal processor (DSP), the hardware accelerator being configured to selectively lock and unlock each of a plurality of global feasibility variables based on a power requirement of the hardware accelerator, the plurality of global feasibility variables respectively corresponding to distinct power modes of the system on chip;
a means for dynamically defining a feasibility of entering a low power mode of operation based on at least said hardware accelerator dynamically locking or unlocking one or more of the global feasibility variables; and
a means for entering or exiting from a low power mode based on said defined feasibility,
wherein a communication channel exists between firmware of the DSP and the native operative system running on central processor core through which the DSP firmware provides an estimate of its power needs to the native operating system running on the central processor.
15. A system on chip as claimed in claim 14 , wherein the DSP firmware can selectively lock and unlock said feasibility variables through said data communication channel with the native operating system depending upon its power requirements.
16. A system on chip as claimed in claim 14 , wherein said DSP firmware uses a ring buffer approach for reducing power related to data communication with the native operating system.
17. A system on chip as claimed in claim 16 , wherein four buffers are used in said ring buffer approach.
18. A system on chip as claimed in claim 14 , further comprising:
a resource manager for estimating the power needs of said hardware accelerator and communicating the same to the native operating system.
19. A system on chip as claimed in claim 18 , wherein said DSP firmware provides estimate of its power requirement to said resource manager which helps the resource manager to accurately estimate an exact power requirement of hardware accelerator.
20. A system on chip with efficient power management, comprising:
a central processor;
a power scheduler running on said central processor for power management of the system on chip;
a plurality of other processors, each processor being configured to selectively lock and unlock each of a plurality of global feasibility variables based on a power requirement of the processor, the plurality of global feasibility variables respectively corresponding to distinct power modes of the system on chip;
a means for dynamically defining a feasibility of entering a low power mode of operation based on at least one of said other processors dynamically locking or unlocking one or more of the global feasibility variables;
a means for entering or exiting from a low power state based on said defined feasibility; and
a resource manager for estimating power needs of at least one of said other processors and communicating the same to the power scheduler for efficient power management.
21. A system on chip as claimed in claim 20 , wherein said locking/unlocking is done by incrementing/decrementing the feasibility variables.