Block-by-block leakage control and interface
View Patent ↗In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode.
1. A leakage reduction circuit, comprising:
a virtual ground node;
a plurality of leaking transistors coupled between the virtual ground node and a power supply node;
a first NMOS transistor coupled between the virtual ground node and a ground node, the first NMOS transistor having its gate driven by an enable signal asserted during normal operation of the plurality of leaking transistors;
a second NMOS transistor having a drain to the virtual ground node, the second NMOS transistor having its gate driven by a standby signal asserted during a standby mode for the plurality of leaking transistors; and
a native NMOS transistor coupled between a source of the second NMOS transistor and the ground node, the native NMOS transistor having a gate driven by the virtual ground node, wherein the first NMOS transistor is sized so as to supply a necessary current during normal operation and wherein the second NMOS transistor is smaller than the first NMOS transistor such that a voltage for the virtual ground node raises above ground to reduce leakage by the plurality of leaking transistors during the standby mode.
2. A method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays, wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed, comprising:
providing a leakage control circuit corresponding to each sub-array, wherein each leakage control circuit includes: a first NMOS transistor coupled between the virtual ground node and a ground node, the first NMOS transistor having its gate driven by an enable signal asserted during normal operation of the plurality of leaking transistors; a second NMOS transistor having a drain to the virtual ground node, the second NMOS transistor having its gate driven by a standby signal asserted during a standby mode for the plurality of leaking transistors; and a native NMOS transistor coupled between a source of the second NMOS transistor and the ground node, the native NMOS transistor having a gate driven by the virtual ground node, wherein the first NMOS transistor is sized so as to supply a necessary current during normal operation and wherein the second NMOS transistor is smaller than the first NMOS transistor such that a voltage for the virtual ground node raises above ground to reduce leakage by the plurality of leaking transistors during the standby mode; and
asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode by de-asserting the standby and the enable signals for the leakage control circuit corresponding to the sub-array.