Output impedance insensitive power amplifier architecture
View Patent ↗An apparatus and method for adapting a power amplifier to a variable load includes comparing the actual output power to the expected output power, modifying a drive signal to the power amplifier, measuring the value of at least one electrical parameter, determining the difference between the measured value and a predetermined value, and periodically adjusting the drive signal according to the difference. The parameters modified include, but are not limited to, the power delivered to the input of the power amplifier, the DC power supply voltage to any stage of the power amplifier, and the current setting bias values.
1. An amplifier system, comprising:
a power amplifier;
a directional coupler coupled to an output of the power amplifier;
a bias network coupled to the power amplifier; and
a bias point controller coupled to the bias network through a bi-directional communication link, the bias point controller configured to receive power level data corresponding to amplifier output power detected in the directional coupler, and further configured, upon encountering an unexpected power level, to engage an algorithm that determines one of a plurality of techniques for returning the unexpected power level to an expected power level.
2. The amplifier system of claim 1 , wherein the plurality of techniques comprises adjusting at least one of a) an average drain-source current of a FET that is a part of the power amplifier, b) an average drain-source voltage of the FET, c) an average gate-source voltage of the FET, or d) input power applied to the power amplifier.
3. The amplifier system of claim 1 , wherein the bias network is coupled to an input of the power amplifier through a first decoupling and matching network.
4. The amplifier system of claim 3 , wherein the bias network is further coupled to the output of the power amplifier through a second decoupling and matching network.
5. A method of controlling an amplifier, the method comprising:
detecting a power level at an output of the amplifier;
determining if the detected power level is at an unexpected power level as a result of a change in output impedance load on the amplifier; and
compensating for the change in output impedance load by varying a characteristic load line of the amplifier, the varying comprising:
engaging an algorithm that determines which one specific technique amongst a plurality of techniques should be used to change a bias point of the amplifier for varying the characteristic load line and returning the unexpected power level to an expected power level.
6. The method of claim 5 , wherein the plurality of techniques comprises at least one of a) adjusting an average drain-source current of a FET that is a part of the amplifier, b) adjusting an average drain-source voltage of the FET, c) adjusting an average gate-source voltage of the FET, or d) adjusting input power applied to the amplifier.
7. The method of claim 5 , wherein detecting the power level at the output of the amplifier comprises detecting at least one of a forward power level P f or a reflected power level P r at the output of the amplifier.