Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit provided with an (m×n)-bit output mode and an n-bit output mode and including a set of (m×n) I/O portions 103 for outputting signals to the outside, wherein data with a bus width of (m×n) bits are selected by a set of selectors 101 in the (m×n)-bit output mode so that the data with the bus width of (m×n) bits are outputted from the set of (m×n) I/O portions 103 whereas data with a bus width of n bits are multiply selected by the set of selectors 101 in the n-bit output mode so that the data with the bus width of n bits are outputted from the set of (m×n) I/O portions 103 while multiplexed in at least two I/O portions per bit. Every I/O portions which output one and the same bit are short-circuited externally to improve current drive capacity.
1. A semiconductor integrated circuit provided with a plurality of output modes including a variable (m×n) bit output mode, in which m is a natural number not smaller than 2, and n is a natural number; and an n-bit output mode, comprising:
(m×n) input/output I/O portions outputting signals to the outside;
wherein in the variable (m×n)-bit output mode, the (m×n) I/O portions output data for a bus width of (m×n) bits; and
in the n-bit output mode, the (m×n) I/O portions output data for a bus width of n bits,
wherein in the n-bit output mode, at least two of the (m×n) I/O portions outputs the same data simultaneously for each of said n bits,
wherein:
in the case where m is equal to 2, a 2n-bit output mode and an n-bit output mode are provided;
in the 2n-bit output mode, s-th one (1≦s≦2n) of 2n I/O portions outputting data with a bus width of 2n bits outputs an s-th bit of data with the bus width of 2n bits; and
in the n-bit output mode, (2t−1)-th and 2t-th ones (1≦t≦n) of 2n I/O portions output a t-th bit of data with the bus width of n bits.
2. The semiconductor integrated circuit according to claim 1 , further comprising:
first selectors for selecting signals to be transferred to the I/O portions respectively; and
each of the first selectors selects one bit from data with the bus width of (m×n) bits in the (m×n)-bit output mode whereas each of the first selectors selects one bit from data with the bus width of n bits in the n-bit output mode.
3. The semiconductor integrated circuit according to claim 2 , wherein:
the first selectors include (n−1) sets of m selectors, and a set of (m−1) selectors; and
the selectors select different bits respectively from data with the bus width of (m×n) bits in the (m×n)-bit output mode whereas each set of selectors select one and the same bit from data with the bus width of n bits in the n-bit output mode.
4. The semiconductor integrated circuit according to claim 1 , further comprising:
(m×n) tristate buffers driving the (m×n) I/O portions respectively;
wherein, in the n-bit output mode, (k×n) tristate buffers (in which k is a natural number not smaller than 1 but smaller than m) among the (m×n) tristate buffers become high in impedance.
5. The semiconductor integrated circuit according to claim 1 , wherein the (m×n) I/O portions are bidirectional I/O portions provided with (m×n) input buffers respectively.
6. The semiconductor integrated circuit according to claim 1 , further provided with an output mode that outputs a signal different from the data at the same time, comprising:
first selectors selecting signals to be transferred to the I/O portions respectively; and
second selectors selecting signals to be inputted to the first selectors respectively;
wherein each of the first selectors selects one bit from data with the bus width of (m×n) bits in the variable (m×n) bit output mode for outputting the data with the bus width of the (m×n) bits whereas the first selectors select bits corresponding to signals outputted from the second selectors in the variable n-bit output mode for outputting the data with the bus width of the n bits and the output mode that outputs a signal different from the data at the same time;
in the variable n-bit output mode for outputting the data with the bus width of the n bits, each of second selectors selects one bit from data with the bus width of n-bits; and
in the output mode that outputs a signal different from the data at the same time, each of the second selectors selects a signal different from the data with the bus width of (m×n)-bits and different from the data with the bus width of n-bits.
7. The semiconductor integrated circuit according to claim 1 , further comprising:
(2n−1) selectors, provided so as to correspond to second to 2n-th ones of the 2n I/O portions;
wherein in the 2n-bit output mode, an s-th selector selects the s-th bit of data with the bus width of 2n bits; and
in the n-bit output mode, (2t−1)-th and 2t-th selectors select the t-th bit of data with the bus width of n bits.
8. The semiconductor integrated circuit according to claim 1 , wherein ascending order of the (m×n) I/O portions can be switched over to descending order by setting, and vice versa.