SRAM memory device with improved write operation and method thereof

1. An SRAM memory information storage device powered by a supply voltage for the storage device, the storage device comprising:

an array of base cells, organized in base columns and powered by a power supply voltage; and

means for varying the power supply voltage for the base column for a base cell selected for information storage,

wherein the means for varying the power supply voltage for the base column comprises:

emulation means, in a mirror column comprising at least one mirror cell provided with internal nodes, for the most restricting cell in writing in the base column comprising the selected base cell;

means for varying a mirror power supply voltage for the mirror column; and

means for copying the mirror power supply voltage in the base column comprising the selected base cell.

2. The storage device according to claim 1 ,

wherein the mirror column comprises at least one other mirror cell so as to constitute a number P of mirror cells placed in parallel and a number N of activated mirror access transistors, and

the ratio N/P between the number of activated mirror access transistors and the number of mirror cells placed in parallel depends on the supply voltage for the storage device.

3. The storage device according to claim 1 , wherein the means for varying the mirror power supply voltage comprises a feedback loop connected to at least one of the internal nodes.

4. The storage device according to claim 1 , wherein at least one mirror cell in the mirror column is an SRAM cell comprising access transistors and core transistors, the threshold voltage of at least one of the transistors of the SRAM cell being different from the threshold voltage of a transistor of the same type in the base cells.

5. The storage device according to any one of the previous claims, further comprising means for creating an overvoltage on at least one line of bits.

6. The storage device according to claim 5 ,

wherein the selected base cell is associated with a pair of lines of bits, and

the means for creating an overvoltage creates an overvoltage on at least one of the lines of bits of the pair of lines of bits.

7. An SRAM memory information storage device powered by a supply voltage for the storage device, the storage device comprising:

an array of base cells, organized in base columns and powered by a power supply voltage;

means for varying the power supply voltage for the base column of a base cell selected for information storage; and

means for, during a phase of a write operation in which information is effectively written into the selected base cell, creating an overvoltage on at least one line of bits in the base column comprising the selected base cell.

8. The storage device according to claim 7 ,

wherein the selected base cell is associated with a pair of lines of bits, and

during the phase of the write operation in which information is effectively written into the selected base cell, the means for creating an overvoltage creates an overvoltage on at least one of the lines of bits of the pair of lines of bits.

9. The storage device according to claim 7 ,

wherein the selected base cell is associated with a pair of lines of bits, and

the means for creating an overvoltage creates the overvoltage on at least one of the lines of bits of the pair of lines of bits after that one line of bits has changed to 0.

10. The storage device according to claim 7 , wherein the means for creating an overvoltage creates the overvoltage on the at least one line of bits in the base column comprising the selected base cell after pre-charging of the at least one line of bits has ended.

11. The storage device according to claim 7 ,

wherein the selected base cell is associated with a pair of lines of bits, and

the means for creating an overvoltage creates the overvoltage after the pair of lines of bits are at the values to be written to internal nodes of the selected base cell.

12. The storage device according to claim 7 , wherein the overvoltage created by the means for creating an overvoltage is a negative overvoltage.

13. An SRAM memory information storage device powered by a supply voltage for the storage device, the storage device comprising:

an array of base cells, organized in base columns and powered by a power supply voltage;

a first circuit adapted to vary the power supply voltage for the base column of a base cell selected for information storage; and

a second circuit adapted to, during a phase of a write operation in which information is effectively written into the selected base cell, create an overvoltage on at least one line of bits in the base column comprising the selected base cell,

wherein the second circuit creates the overvoltage on the at least one line of bits in the base column comprising the selected base cell after pre-charging of the at least one line of bits has ended.

14. The storage device according to claim 13 ,

wherein the selected base cell is associated with a pair of lines of bits, and

the second circuit creates the overvoltage on at least one of the lines of bits of the pair of lines of bits after that one line of bits has changed to 0.

15. The storage device according to claim 13 ,

wherein the selected base cell is associated with a pair of lines of bits, and

during the phase of the write operation in which information is effectively written into the selected base cell, the second circuit creates an overvoltage on at least one of the lines of bits of the pair of lines of bits.

16. The storage device according to claim 13 ,

wherein the selected base cell is associated with a pair of lines of bits, and

the second circuit creates the overvoltage after the pair of lines of bits are at the values to be written to internal nodes of the selected base cell.

17. The storage device according to claim 13 , wherein the overvoltage created by the second circuit is a negative overvoltage.