Service processor host flash update over LPC

1. A method for updating contents of a BIOS ROM comprising:

disconnecting a host system from the BIOS ROM;

disconnecting the Southbridge from the LPC bus;

mastering the LPC bus with the service processor;

transferring data from a service processor to the BIOS ROM;

using an LPC bus to transfer data from the service processor to the BIOS ROM; and

updating the contents of the BIOS ROM using the transferred data,

wherein control of the LPC bus is switched from the Southbridge to the service processor,

wherein mastering of the LPC bus by the service processor comprises incorporating an LPC master function in a Southbridge into the service processor, and

wherein the LPC master function is integrated into the Southbridge circuitry.

2. The method of claim 1 , further comprising holding a host system in reset while updating the contents of the BIOS ROM.

3. The method of claim 1 , further comprising turning off a host system prior to updating the contents of the BIOS ROM.

4. The method of claim 1 , wherein the LPC master function for the service processor is accomplished using an FPGA.

5. The method of claim 1 , further comprising disconnecting the Southbridge from the LPC bus using a plurality of quick switches.

6. The method of claim 1 , further comprising:

updating the service processor via an Ethernet connection; and

transmitting update data from the updated service processor to the BIOS ROM.

7. The method of claim 1 , further comprising using a clock gating logic to stop an LPC clock signal from the LPC bus to the BIOS ROM.