Tri-gate field-effect transistors formed by aspect ratio trapping
View Patent ↗Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
1. A method for forming a structure, the method comprising the steps of:
forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, a crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the crystalline material.
2. The method of claim 1 , wherein the second and third semiconductor materials have different lattice constants.
3. The method of claim 2 , wherein the second semiconductor material is relaxed and the third semiconductor material is strained.
4. The method of claim 1 , wherein removing a portion of the dielectric layer comprises exposing at least a portion of a sidewall of the second layer.
5. The method of claim 1 , wherein the second semiconductor material comprises SiGe.
6. The method of claim 5 , wherein the third semiconductor material comprises at least one of Si and Ge.
7. The method of claim 1 , wherein the second semiconductor material has a bandgap of at least 0.5 eV.
8. The method of claim 7 , wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.
9. The method of claim 8 , wherein the second semiconductor material comprises at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, or CdTe.
10. The method of claim 1 , wherein the third semiconductor material has a bulk electron mobility greater than 2000 cm 2 /V·s.
11. The method of claim 10 , wherein the third semiconductor material comprises at least one of InSb, InAs, or InGaAs.
12. The method of claim 1 , wherein a difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material is less than 1%.
13. A method for forming a structure, the method comprising the steps of:
forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, at least one crystalline material layer comprising a second semiconductor material having a lattice mismatch with the first semiconductor material, a majority of dislocation defects in the second semiconductor material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the crystalline material.
14. The method of claim 13 , wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.
15. The method of claim 13 , wherein the second semiconductor material has a bandgap of at least 0.5 eV.
16. The method of claim 13 , wherein the second semiconductor material has a bulk electron mobility greater than 2000 cm 2 /V·s.
17. The method of claim 13 , wherein the at least one crystalline material layer includes a first layer comprising the second semiconductor material and a second layer comprising a third semiconductor material.
18. The method of claim 17 , wherein the third semiconductor material comprises at least one of a III-V compound or a II-VI compound, and the third semiconductor material is different from the second semiconductor material.
19. The method of claim 17 , wherein the second and third semiconductor materials have different lattice constants.
20. The method of claim 17 , wherein the second semiconductor material is relaxed and the third semiconductor material is strained.
21. The method of claim 17 , wherein the third semiconductor material includes at least one element contained in the second semiconductor material.
22. The method of claim 13 , wherein defining the dielectric layer comprises at least one of thermal oxidation or PECVD.
23. A method for forming a structure, the method comprising:
removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin;
depositing a dielectric layer over the substrate and the fin;
planarizing the dielectric layer such that a top surface thereof is substantially co-planar with a top surface of the fin;
defining a trench by removing at least a portion of the fin, the trench having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, a crystalline material comprising a second semiconductor material lattice-mismatched to the first semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the second semiconductor material.