Device and process involving pinhole undercut area
An electronic device fabrication method including: (a) providing a dielectric region and a lower electrically conductive region, wherein the dielectric region includes a plurality of pinholes each with an entry and an exit; and (b) depositing an etchant for the lower electrically conductive region into the pinholes that undercuts the pinholes to create for a number of the pinholes an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit.
1. An electronic device comprising:
(a) a dielectric region including a plurality of pinholes, each pinhole having an entry and an exit;
(b) an upper electrically conductive region over the dielectric region, and comprising an upper electrically conductive region material; and
(c) a lower electrically conductive region under the dielectric region,
wherein at least some of the pinholes are undercut with an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit; and
wherein the upper electrically conductive region material is present in the pinholes but in a number of the pinholes, the upper electrically conductive region material fails to bridge the undercut area to contact the lower electrically conductive region.
2. The electronic device of claim 1 , wherein the upper electrically conductive region comprises a semiconductor region and a number of electrodes.
3. The electronic device of claim 1 , wherein the lower electrically conductive region comprises a semiconductor region and a number of electrodes.
4. The electronic device of claim 1 , wherein the electronic device is a transistor array having a failure rate that is less than about 5% due to dielectric failure.
5. The electronic device of claim 1 , wherein the dielectric region has a thickness ranging from about 100 nm to about 500 nm.
6. The electronic device of claim 1 , wherein the lower electrically conductive region comprises aluminum, chromium, copper, gold, indium, nickel, platinum, silver, titanium, or a mixture thereof.
7. A thin film transistor comprising:
(a) a dielectric region;
(b) an upper electrically conductive region over the dielectric region;
(c) a lower electrically conductive region below the dielectric region; and
(d) a plurality of pinholes in the dielectric region, each pinhole having an entry and an exit, and each pinhole extending between the upper electrically conductive region and the lower electrically conductive region;
wherein at least some of the pinholes are undercut with an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit; and
wherein no electrical connection is made between the lower electrically conductive region and the upper electrically conductive region through the at least some of the pinholes.
8. The thin film transistor of claim 7 , wherein the upper electrically conductive region comprises a semiconductor region and a number of electrodes.
9. The thin film transistor of claim 7 , wherein the lower electrically conductive region comprises a semiconductor region and a number of electrodes.
10. The thin film transistor of claim 7 , wherein the thin film transistor exhibits an improvement in the current on/off ratio of at least about 10 times.
11. The thin film transistor of claim 7 , wherein the dielectric region has a thickness ranging from about 100 nm to about 500 nm.
12. The thin film transistor of claim 7 , wherein the lower electrically conductive region comprises aluminum, chromium, copper, gold, indium, nickel, platinum, silver, titanium, or a mixture thereof.
13. A thin film transistor comprising:
(a) a dielectric region;
(b) an upper electrically conductive region over the dielectric region;
(c) a lower electrically conductive region; and
(d) at least one pinhole in the dielectric region, the pinhole having an entry and an exit, and extending between the upper electrically conductive region and the lower electrically conductive region;
wherein the at least one pinhole is undercut with an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit; and
wherein no electrical connection is made between the lower electrically conductive region and the upper electrically conductive region through the at least one pinhole.