Multi-mode pulse width modulated displays
Methods, apparatus, and pulse width modulating a display include receiving image data and generating pulse data to be written to rows of pixels in a display. The data include a pulse width modulated drive sequence that writes data to selected rows on a first phase of a clock and terminates a write operation on a different row on a second phase of the clock.
1. A projection display system comprising:
an illumination source with optics to direct that illumination to a display component;
projection optics to direct light from a display component to a display screen; and
a display component system comprising a display component and display controller, wherein the display component is modulated by data from the display controller, said data comprising a pulse width modulated drive sequence that writes data to a selected row and terminates a write operation on a different row; wherein the terminating write operation comprises writing all elements in a row to a single predetermined value, thereby terminating the duration of the pulse width modulation on that row by a deterministic time comprising at least a fraction of a least significant bit.
2. The projection display system of claim 1 , wherein the predetermined value corresponds to a black level of the display.
3. The projection display system of claim 1 , wherein the pixels comprise liquid crystal on silicon elements.
4. The projection display system of claim 1 , wherein the display component is a nematic liquid crystal display.
5. A controller for a pulse width modulated display, the controller comprising:
a voltage controller that provides at least one voltage supply that is applied to pixels in a display; and
a processor that receives image data and generates data to be written to rows of pixels in the display,
wherein the data to be delivered comprises a pulse width modulated drive sequence that writes data to a selected row and terminates a write operation on a different row; wherein the terminating write operation comprises writing all elements in a row to a single predetermined value, thereby terminating the duration of the pulse width modulation on that row by a deterministic time comprising at least a fraction of a least significant bit.
6. The controller of claim 5 , wherein the predetermined value corresponds to a black level of the display.
7. The controller of claim 5 , wherein the predetermined value corresponds to a white level of the display.
8. The controller of claim 5 , wherein the image data comprises a gray scale command.
9. The controller of claim 5 , wherein the image data comprises multiple color image data.
10. The controller of claim 5 , wherein the pulse width modulated display is a nematic liquid crystal display.
11. The controller of claim 5 , wherein the data received by the controller is digital image data.
12. A method for providing a modulation drive sequence for a pulse width modulated display, the method comprising:
receiving a row write address;
receiving a second row write address and a terminating value to be written to the second row;
writing data to an addressed row in a display; and
terminating a write operation on the second row; wherein the terminating write operation comprises writing all elements in a row to a single predetermined value, thereby terminating the duration of the pulse width modulation on that row by a deterministic time comprising at least a fraction of a least significant bit.
13. The method of claim 12 , wherein the predetermined value corresponds to a black level of the display.
14. The method of claim 12 , wherein the predetermined value corresponds to a white level of the display.
15. The method of claim 12 , wherein writing data to the addressed row comprises applying pulse width modulated signals to pixels in the row.
16. The method of claim 12 , wherein the data address is received on one clock phase and the data address for the terminating write operation is received on a subsequent clock phase.
17. The method of claim 16 , wherein the first clock phase is a rising edge of a clock cycle and the subsequent clock phase is a falling edge of a clock cycle.
18. The method of claim 12 , wherein the pulse width modulated display is a nematic liquid crystal display.
19. A display comprising:
an array of pixel elements;
a voltage controller that provides at least one voltage supply that is applied to the pixels in the display; and
a processor that receives image data and generates data to be written to rows of pixels in the display, wherein the data comprises a pulse width modulated drive sequence that writes data to a selected row and terminates a write operation on a different row; wherein the terminating write operation comprises writing all elements in that row to a single predetermined value, thereby terminating the duration of the pulse width modulation on that row by a deterministic time comprising at least a fraction of a least significant bit.
20. The display of claim 19 , wherein the predetermined value corresponds to a black level of the display.
21. The display of claim 19 , wherein the predetermined value corresponds to a white level of the display.
22. The display of claim 19 , wherein the pixels comprise liquid crystal on silicon elements.
23. The display of claim 19 , wherein the image data comprises a gray scale command.
24. The display of claim 19 , wherein the image data comprises multiple color image data.
25. The display of claim 19 , wherein said display is a nematic liquid crystal display.