Thin film transistor array panel and manufacturing method thereof
View Patent ↗The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
1. A thin film transistor array panel comprising:
an insulating substrate;
a channel layer including an oxide material formed on the insulating substrate;
a gate insulating layer formed on the channel layer;
a gate electrode formed on the gate insulating layer;
an interlayer insulating layer formed on the gate electrode;
a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer formed on the first conductive layer;
a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer formed on the first conductive layer;
a pixel electrode comprising the first conductive layer; and
a passivation layer formed on the data line and the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein
the passivation layer extends above the data line, and includes a protruded portion covering the drain electrode.
3. The thin film transistor array panel of claim 1 , further comprising:
a spacer formed on the passivation layer,
wherein the spacer has the same planar shape as the passivation layer.
4. The thin film transistor array panel of claim 1 , further comprising:
a spacer formed on the passivation layer,
wherein the spacer covers less than all of the passivation layer.
5. The thin film transistor array panel of claim 4 , wherein
the gate insulating layer has substantially the same planar shape as the channel layer.
6. The thin film transistor array panel of claim 1 , further comprising:
a storage electrode line formed on a portion of the substrate, except on the gate insulating layer, and intersecting the data line.
7. The thin film transistor array panel of claim 1 , further comprising:
a color filter formed on the pixel electrode.
8. The thin film transistor array panel of claim 1 , further comprising:
a color filter formed between the interlayer insulating layer and the pixel electrode.
9. The thin film transistor array panel of claim 1 , further comprising:
a color filter formed between the substrate and the channel layer.
10. The thin film transistor array panel of claim 1 , wherein the gate insulating layer has substantially the same planar shape as the channel layer.
11. The thin film transistor array panel of claim l 0 , further comprising:
a storage electrode line formed on the substrate.
12. The thin film transistor array panel of claim 10 , further comprising:
a color filter formed on the pixel electrode.
13. The thin film transistor array panel of claim 10 , further comprising:
a color filter formed between the interlayer insulating layer and the pixel electrode.
14. The thin film transistor array panel of claim 10 , further comprising:
a color filter formed between the substrate and the channel layer.
15. A thin film transistor array panel comprising:
an insulating substrate;
a channel layer including an oxide material formed on the insulating substrate;
a gate insulating layer formed on the channel layer;
a gate line formed on the gate insulating layer;
an interlayer insulating layer formed on the gate line;
a data line including a source electrode and a drain electrode formed on the interlayer insulating layer;
a pixel electrode formed on the interlayer insulating layer, and connected to the drain electrode;
a passivation layer formed on the data line and the drain electrode; and
a spacer formed on the passivation layer,
wherein the passivation layer is coextensive with the data line and includes a portion covering the drain electrode, and
at least a part of a boundary of the spacer is the same as a boundary of the passivation layer.
16. The thin film transistor array panel of claim 15 , wherein the spacer has the substantially same planar shape as the passivation layer.
17. The thin film transistor array panel of claim 15 , wherein the spacer covers less than all of the passivation layer.
18. The thin film transistor array panel of claim 1 , wherein the first conductive layer comprises a transparent conducting oxide and the second conductive layer comprises a metal.