Apparatus and methods of integrated-circuit device testing
A motherboard device (MB) interface board (DIB) configured as universal interface to a family of integrated circuit (IC) devices provides the electrical connectivity to automated test equipment (ATE) and physical mating commonality with an IC device handler for reduced time to market and enhanced economy for design validation and production verification testing. In particular, use of one or more daughter cards (DC) that mount to the MB DIB avoid redesign of the entire DIB assembly for a new IC design. Each DC can be more quickly designed at a lower cost than the entire DIB assembly, enabling replacement of any defective site. The DC increases the available surface area for mounting of support components for the device under test (DUT).
1. An apparatus for reduced time to market and enhanced economy for design validation and production verification testing, comprising:
a common device interface board (DIB) sized for and electrically interfaced for being received by automated test equipment and comprising a plurality of card mounting fixtures;
a plurality of daughter cards attached respectively to the corresponding plurality of card mounting fixtures and electrically interfacing thereby to the automated test equipment via the common DIB to form a DIB assembly; and
a test site attached to each of the plurality of daughter cards and positioned by the DIB assembly for receiving a plurality of integrated devices simultaneously from a handler for concurrent testing.
2. The apparatus of claim 1 , further comprising a disengagable attachment between each of the plurality of daughter cards and the common DIB for repair replacement.
3. The apparatus of claim 1 , further comprising a disengagable attachment between each daughter card and the common DIB for replacement of a failed daughter card to facilitate full-rate testing.
4. The apparatus of claim 1 , wherein each card mounting fixture is identical and each daughter card is identical for simplified design and provisioning.
5. The apparatus of claim 1 , wherein the common DIB and the plurality of daughter cards are positioned so as to define a spacing sufficient for mounting electronic components between an undersurface of the plurality of daughter cards and an upper surface of the common DIB, and further comprising electronic components mounted on the undersurface of the plurality of daughter cards for electrically supporting the plurality of integrated devices under test.
6. A method for reduced time to market and enhanced economy for design validation and production verification testing, comprising:
creating a common device interface board (DIB) sized for and electrically interfaced for being received by automated test equipment and presenting a plurality of card mounting fixtures;
attaching a plurality of daughter cards respectively to the corresponding plurality of card mounting fixtures and electrically interfacing thereby to the automated test equipment via the common DIB to form a DIB assembly; and
simultaneously inserting a plurality of integrated devices with a handler for concurrent testing in a test site attached to a respective daughter card.
7. The method of claim 6 , further comprising disengaging the attachment between each of the plurality of daughter cards and the common DIB for repair replacement with another daughter card.
8. The method of claim 6 , further comprising disengaging an attachment between one failed daughter card and the common DIB for replacement with another daughter card to facilitate full-rate testing.
9. The method of claim 6 , further comprising creating an identical plurality of card mounting fixtures and an identical plurality of daughter cards for simplified design and provisioning.
10. The method of claim 6 , further comprising creating the plurality of card mounting fixtures of the common DIB with a support structure spacing an undersurface of the plurality of daughter cards from an upper surface of the common DIB, the spacing corresponding to low profile electrical connectors between the plurality of daughter cards and the common DIB and sufficient for electronic components mounted on the undersurface of the plurality of daughter cards for electrically supporting the plurality of integrated devices under test.
11. An apparatus for reduced time to market and enhanced economy for design validation and production verification testing, comprising:
means for creating a common device interface board (DIB) sized for and electrically interfaced for being received by automated test equipment and presenting a plurality of card mounting fixtures;
means for attaching a plurality of daughter cards respectively to the corresponding plurality of card mounting fixtures and electrically interfacing thereby to the automated test equipment via the common DIB to form a DIB assembly; and
means for simultaneously inserting a plurality of integrated devices with a handler for concurrent testing in a respective test site attached to a respective daughter card.
12. The apparatus of claim 11 , further comprising means for disengaging the attachment between at least one of the plurality of the daughter cards and the common DIB for repair replacement with another daughter card.
13. The apparatus of claim 11 , further comprising means for disengaging an attachment between one failed daughter card and the common DIB for replacement with another daughter card to facilitate full-rate testing.
14. The apparatus of claim 11 , further comprising means for creating an identical plurality of card mounting fixtures and an identical plurality of daughter cards for simplified design and provisioning.
15. The apparatus of claim 11 , further comprising means for creating the card mounting fixture of the common DIB with a support structure spacing an undersurface of the plurality of daughter cards from an upper surface of the common DIB, the spacing corresponding to low profile electrical connectors between the plurality of daughter cards and the common DIB and sufficient for electronic components mounted on the undersurface of the plurality of daughter cards for electrically supporting the plurality of integrated devices under test.