Repeater circuit with staged output

1. An electronic circuit comprising:

a first output stage including a first output circuit and a second output circuit;

a second output stage including a third output circuit and a fourth output circuit;

an activation stage including a first activation circuit and a second activation circuit, wherein the first activation circuit is configured to activate the first output circuit responsive to an input signal transitioning from a first logic level to a second logic level, and wherein the third output circuit is configured to be activated responsive to and at a first delay time subsequent to the first activation circuit activating the first output circuit, wherein each of the first and third output circuits are configured to drive an output signal to a predetermined state on an output node, wherein the predetermined state is based on the input signal;

a deactivation stage including a first deactivation circuit and a second deactivation circuit, wherein the first deactivation circuit is configured to deactivate the first output circuit at a second delay time subsequent to activation of the first output circuit, wherein the third output circuit is configured to be deactivated responsive to and at the first delay time subsequent to the first deactivation circuit deactivating the first output circuit; and

a keeper circuit coupled to provide the predetermined state of the output signal on the output node subsequent to deactivation of the first and third output circuits when the second and fourth output circuits are also inactive.

2. The electronic circuit as recited in claim 1 , wherein the electronic circuit further includes:

an echo stage including a first echo circuit and a second echo circuit, wherein the first echo circuit is configured to drive the input node responsive to and at a first delay time subsequent to the first activation circuit activating the first output circuit, and wherein the first echo circuit is configured to be deactivated responsive to and at the first delay time subsequent to the first deactivation circuit deactivating the first output circuit;

wherein the second activation circuit is configured to activate the second output circuit responsive to the input signal transitioning from the second logic level to the first logic level, and wherein the fourth output circuit is configured to be activated responsive to and at the first delay time subsequent to the second activation circuit activating the second output circuit, wherein each of the second and fourth output circuits are configured to drive the output signal on an output node;

wherein the second echo circuit is configured to drive the input node responsive to and at a first delay time subsequent to the second activation circuit activating the second output circuit;

wherein the second deactivation circuit is configured to deactivate the second output circuit at the second delay time subsequent to activation of the second output circuit, wherein the fourth output circuit and the second echo circuit are configured to be deactivated responsive to and at the first delay time subsequent to the second deactivation circuit deactivating the second output circuit; and

wherein the keeper circuit is configured to provide and maintain the output signal on the output node at the first logic level subsequent to deactivation of the second and fourth output circuits when the input signal remains at the first logic level, and further to provide and maintain the output signal at the second logic level on the output node subsequent to deactivation of the first and third output circuits when the input signal remains at the second logic level.

3. The electronic circuit as recited in claim 2 , wherein the first activation circuit is configured to inhibit activation of the first output circuit responsive to the input signal transitioning from the second logic level to the first logic level.

4. The electronic circuit as recited in claim 2 further comprising:

a first feedback path coupling the first output circuit to the first deactivation circuit; and

a second feedback path coupling the second output circuit to the second deactivation circuit.

5. The electronic circuit as recited in claim 4 , further comprising:

a first feed-forward circuit coupled between the input node and the first deactivation circuit, wherein the second deactivation circuit is configured to activate responsive to receiving signals from the first feed-forward circuit and the first feedback path; and

a second feed-forward circuit coupled between the input node and the second deactivation circuit, wherein the second deactivation circuit is configured to activate responsive to receiving signals from the second feed-forward circuit and the second feedback path.

6. The electronic circuit as recited in claim 1 further comprising a keeper circuit, wherein the keeper circuit is configured to provide the output signal on the output node at the second logic level subsequent to deactivation of the first and third output circuits.

7. The electronic circuit as recited in claim 6 , wherein the keeper circuit is coupled between the input node and the output node, and wherein the keeper circuit includes a plurality of inverters coupled together in series.

8. The electronic circuit as recited in claim 1 , wherein the second activation circuit is configured to inhibit activation of the second output circuit responsive to the input signal transitioning from the first logic level to the second logic level.

9. The electronic circuit as recited in claim 1 , wherein the first logic level is a logic low level and wherein the second logic level is a logic high level.

10. The electronic circuit as recited in claim 2 , wherein, in the absence of a change of the logic level of the input signal from a first cycle to a second cycle, the first, second, third and fourth output circuits and the first and second echo circuits are configured to remain inactive during the second cycle.

11. A method comprising:

detecting a transition of an input signal on an input node from a first logic level to a second logic level;

an activation circuit activating a first output circuit responsive to said detecting, wherein activating the first output circuit causes the first output circuit to drive an output signal on an output node;

activating a second output circuit responsive to and at a first delay time subsequent to the activation circuit activating the first output circuit, wherein activating the second output circuit causes the second output circuit to drive the output signal at a predetermined state on the output node, wherein the predetermined state is based on the input signal;

a deactivation circuit deactivating the first output circuit at a second delay time subsequent to activating the first output circuit;

deactivating the second output circuit responsive to and at the first delay time subsequent to the deactivation circuit deactivating the first output circuit; and

a keeper circuit providing the predetermined state of the output signal on the output node subsequent to deactivation of the first and second output circuits when the second and fourth output circuits are also inactive.

12. The method as recited in claim 11 further comprising:

activating a first echo circuit responsive to and at the first delay time subsequent to the activation circuit activating the first output circuit;

deactivating the first echo circuit responsive to and at the first delay time subsequent to the deactivation circuit deactivating the first output circuit;

detecting a transition of the input signal on the input node from the second logic level to the first logic level;

the activation circuit activating a third output circuit responsive to said detecting the transition from the second logic level to the first logic level, wherein activating the second output circuit causes the third output circuit to drive the output signal on the output node;

activating a fourth output circuit and a second echo circuit responsive to and at the first delay time subsequent to the activation circuit activating the third output circuit, wherein activating the second echo circuit causes the second echo circuit to drive the input node, and wherein activating the fourth output circuit causes the fourth output circuit to drive the output signal on the output node;

the deactivation circuit deactivating the third output circuit at the first delay time subsequent to activating the third output circuit;

deactivating the second echo circuit and the fourth output circuit responsive to and at the first delay time subsequent to the deactivation circuit deactivating the third output circuit;

providing the output signal at the second logic level on the output node using the keeper circuit subsequent to deactivating the first and second output circuits when the input signal remains at the second logic level; and

providing the output signal at the first logic level on the output node using the keeper circuit subsequent to deactivating the third and fourth output circuits when the input signal remains at the first logic level.

13. The method as recited in claim 12 , further comprising inhibiting activation of the first output circuit, the second output circuit, and the first echo circuit responsive to the input signal transitioning from the second logic level to the first logic level.

14. The method as recited in claim 12 , further comprising inhibiting activation of the third output circuit, the fourth output circuit, and the second echo circuit responsive to the input signal transitioning from the first logic level to the second logic level.

15. The method as recited in claim 12 , further comprising, in the absence of a change of the logic level of the input signal from a first cycle to a second cycle, maintaining the first, second, third and fourth output circuits and the first and second echo circuits in an inactive state during the second cycle.

16. An electronic circuit comprising:

a first output circuit configured to drive an output signal on an output node, the first output circuit including first and second output devices;

an activation circuit configured to activate the first output circuit responsive to detecting a logical transition of an input signal on an input node;

a second output circuit configured to drive the output signal on the output node, wherein the second output circuit is configured to be activated, after a first delay time, responsive to the activation circuit activating the first output circuit, wherein the first and second output circuits are configured to drive the output signal to a predetermined state based on the input signal, wherein the second output circuit includes third and fourth output devices; and

a deactivation circuit, wherein the deactivation circuit is configured to deactivate the first output circuit at a second delay time subsequent to activation of the first output circuit;

wherein the second output circuit is configured to be deactivated, after the first delay time, responsive to deactivation of the first output circuit; and

a keeper circuit coupled to provide the predetermined state of the output signal on the output node subsequent to deactivation of the first and second output circuits.

17. The electronic circuit as recited in claim 16 , further comprising an echo circuit, wherein the echo circuit is configured to be activated at substantially the same time as the second output circuit and responsive to activation of the first output circuit, wherein, when activated, the echo circuit is configured to drive the input node.

18. The electronic circuit as recited in claim 17 , wherein the echo circuit is further configured to be deactivated at substantially the same time as the second output circuit and responsive to deactivation of the first output circuit.

19. The electronic circuit as recited in claim 16 , further comprising a feed-forward circuit coupled between the input node and the deactivation circuit, wherein the deactivation circuit is configured to deactivate the first output circuit responsive to signals received from the feed-forward circuit and signals received from a feedback path coupled between the activation stage and the deactivation stage.

20. The method as recited in claim 16 , wherein, in the absence of a change of the logic level of the input signal from a first cycle to a second cycle, the first and second output circuits are configured to remain inactive during the second cycle.