Manufacturing process for a photodetector

1. A manufacturing process for a photo-detector, comprising:

(a) providing a germanium substrate with a plane including a first processing area and a second processing area which are both on the plane;

(b) defect-reduction processing only one of the first processing area and the second processing area; and

(c) forming metal-insulator-semiconductor photo-detector elements on the germanium substrate to achieve a multi-wavelength photo-detection on a single chip.

2. A manufacturing process as claimed in claim 1 , wherein the metal-insulator-semiconductor photo-detector element comprises a first metal electrode and a second metal electrode and the manufacturing process further comprises a step of:

providing a bias through a power source including a first electrode and a second electrode, wherein the first electrode is connected to the first metal electrode and the second electrode is connected to the second metal electrode for generating a quantum tunneling effect, so that the photo-detector generates a light current upon being illuminated.

3. A manufacturing process as claimed in claim 2 , further comprising steps of:

forming two metal-insulator-semiconductor photo-detector elements on the germanium substrate; and

switching the second electrode into connecting one of the two second metal electrodes.

4. A manufacturing process as claimed in claim 1 , wherein the step (a) further comprises steps of:

(a1) implanting hydrogen ions into the germanium substrate to form an implanting layer;

(a2) providing a carrier substrate and bonding the germanium substrate thereto; and

(a3) heating the germanium substrate at a temperature ranged from 100° C.˜600° C., wherein the carrier substrate is a glass substrate.

5. A manufacturing process as claimed in claim 4 , wherein the germanium substrate is one selected from a group consisting of a mono-crystalline germanium substrate, a poly-crystalline germanium substrate, a non-crystalline germanium substrate, a non-doping germanium substrate, a P-type doping germanium substrate and an N-type doping germanium substrate.

6. A manufacturing process as claimed in claim 4 , wherein the germanium substrate is one selected from a group consisting of a [100] germanium substrate, a [110] germanium substrate and a [111] germanium substrate.

7. A manufacturing process as claimed in claim 4 , wherein the step (a2) further comprises steps of:

providing a Si substrate; and

forming an insulating layer onto the Si substrate to form the carrier substrate.

8. A manufacturing process as claimed in claim 1 , wherein the defect-reduction processing step (b) is performed by one a dry etching and a wet etching.

9. A manufacturing process as claimed in claim 2 , wherein the germanium substrate comprises a first area, a second area and a third area and the manufacturing process further comprises steps of:

(c11) forming an insulating layer on the first, the second and the third areas;

(c12) forming the second metal electrode on the insulating layer above the second area;

(c13) removing the insulating layer on the first and third areas; and

(c14) forming the first metal electrode on the first and third areas.

10. A manufacturing process as claimed in claim 9 , wherein the insulating layer in the step (c11) is formed by one selected from a group consisting of a low temperature liquid phase deposition, a chemical vapor deposition, a physical vapor deposition, a silicon dioxide deposition and a high-dielectric material deposition.