Granted Patent B2

US 7,915,708 · App. 12/485,528 · Granted Mar 29, 2011

Abstract

Claims (93)

1. A semiconductor device, comprising:

a semiconductor substrate including a main surface;

a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction, one end of each of said plurality of first interconnections connecting to a second interconnection;

a plurality of third interconnections formed in said predetermined region and extending in said predetermined direction, one end of each of said plurality of third interconnections connecting to a fourth interconnection; and

a fifth interconnection located at an edge of said predetermined region, extending in said predetermined direction, and having a fixed potential,

wherein said plurality of first interconnections and said plurality of third interconnections are located in a first plane parallel to said main surface,

said second interconnection, said fourth interconnection, and said fifth interconnection are located in said first plane,

one side of each of said plurality of first interconnections faces each of said plurality of third interconnections, and another side of each of said plurality of first interconnections faces each of said plurality of third interconnections,

an insulating layer is formed on said main surface and fills in between each of said plurality of first interconnections, between each of said plurality of third interconnections, and between one of said plurality of first interconnections and said plurality of third interconnections and said fifth interconnection adjacent to each other,

said plurality of first interconnections, said plurality of third interconnections, and said fifth interconnection are located to align in a direction substantially perpendicular to said predetermined direction,

a capacitance is formed by said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection and said insulating layer formed between each of said plurality of first interconnections and each of said plurality of third interconnections,

said plurality of first interconnections and said second interconnection are one of electrodes of said capacitance, said plurality of third interconnections and said fourth interconnection are the other of said electrodes of said capacitance, and

a plurality of polysilicon films are formed in said predetermined region between said semiconductor substrate and said first plane.

2. The semiconductor device according to claim 1 , wherein

said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection, and said fifth interconnection are formed in a plurality of said first planes spaced apart from each other, and

in plan view, each of said plurality of first interconnections in said first plane overlaps each of said plurality of third interconnections in said first plane adjacent to said first plane.

3. The semiconductor device according to claim 1 , wherein

a plurality of active regions and a plurality of isolation regions are formed in said predetermined region in said semiconductor substrate,

wherein said plurality of polysilicon films are formed at least on said plurality of active regions or said plurality of isolation regions.

4. The semiconductor device according to claim 1 , wherein

said semiconductor substrate includes a first well layer of a first conductivity type extending in said main surface, said fifth interconnection electrically connected to said first well layer,

said first well layer being fixed at one of a ground potential or a power supply potential.

5. The semiconductor device according to claim 4 , wherein

said semiconductor substrate further includes a second well layer of a second conductivity type extending parallel to said first well layer at a position immediately below said predetermined region and apart from said main surface,

said second well layer being fixed at a potential different from the one of the ground potential or the power supply potential at which said first well layer is fixed.

6. The semiconductor device according to claim 1 , wherein

the fifth interconnection includes a plurality of fifth interconnections, and

said plurality of first interconnections and said plurality of third interconnections are formed between said plurality of fifth interconnections.

7. The semiconductor device according to claim 1 , wherein

the plurality of polysilicon films are not electrodes of the capacitance.

8. A semiconductor device, comprising:

a semiconductor substrate including a main surface;

a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction, one end of each of said plurality of first interconnections connecting to a second interconnection;

a plurality of third interconnections formed in said predetermined region and extending in said predetermined direction, one end of each of said plurality of third interconnections connecting to a fourth interconnection; and

a fifth interconnection located at an edge of said predetermined region, extending in said predetermined direction, and having a fixed potential,

wherein said plurality of first interconnections and said plurality of third interconnections are located in a first plane parallel to said main surface,

said second interconnection, said fourth interconnection, and said fifth interconnection are located in said first plane,

one side of each of said plurality of first interconnections faces each of said plurality of third interconnections, and another side of each of said plurality of first interconnections faces each of said plurality of third interconnections,

an insulating layer is formed on said main surface and fills in between each of said plurality of first interconnections, between each of said plurality of third interconnections, and between one of said plurality of first interconnections and said plurality of third interconnections and said fifth interconnection adjacent to each other,

said plurality of first interconnections, said plurality of third interconnections, and said fifth interconnection are located to align in a direction substantially perpendicular to said predetermined direction,

a capacitance is formed by said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection, and said insulating layer formed between each of said plurality of first interconnections and each of said plurality of third interconnections,

said plurality of first interconnections and said second interconnection are one of electrodes of said capacitance, said plurality of third interconnections and said fourth interconnection are the other of said electrodes of said capacitance,

a plurality of conductive films are formed in said predetermined region between said semiconductor substrate and said first plane,

a plurality of active regions and a plurality of isolation regions are formed in said predetermined region in said semiconductor substrate, and

said plurality of conductive films are formed at least on said plurality of active regions or said plurality of isolation regions.

9. The semiconductor device according to claim 8 , wherein

said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection, and said fifth interconnection are formed in a plurality of said first planes spaced apart from each other, and

in plan view, each of said plurality of first interconnections in said first plane overlaps each of said plurality of third interconnections in said first plane adjacent to said first plane.

10. The semiconductor device according to claim 9 , wherein

the plurality of conductive films are not electrodes of the capacitance.

11. The semiconductor device according to claim 8 , wherein

in cross sectional view, each of said plurality of active regions and each of said plurality of isolation regions is arranged alternately to each other.

12. The semiconductor device according to claim 8 , wherein

said semiconductor substrate includes a first well layer of a first conductivity type extending in said main surface, said fifth interconnection electrically connected to said first well layer,

said first well layer being fixed at one of a ground potential or a power supply potential.

13. The semiconductor device according to claim 12 , wherein

said semiconductor substrate further includes a second well layer of a second conductivity type extending parallel to said first well layer at a position immediately below said predetermined region and apart from said main surface,

said second well layer being fixed at a potential different from the one of the ground potential or the power supply potential at which said first well layer is fixed.

14. The semiconductor device according to claim 8 , wherein

the fifth interconnection includes a plurality of fifth interconnections, and

said plurality of first interconnections and said plurality of third interconnections are formed between said plurality of fifth interconnections.

15. A semiconductor device, comprising:

a semiconductor substrate including a main surface;

a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction, one end of each of said plurality of first interconnections connecting to a second interconnection;

a plurality of third interconnections formed in said predetermined region and extending in said predetermined direction, one end of each of said plurality of third interconnections connecting to a fourth interconnection; and

a fifth interconnection located at an edge of said predetermined region, extending in said predetermined direction, and having a fixed potential,

wherein said plurality of first interconnections, said plurality of third interconnections, and said fifth interconnection are located at substantially equal intervals in a first plane parallel to said main surface,

said second interconnection, said fourth interconnection, and said fifth interconnection are located in said first plane,

one side of each of said plurality of first interconnections faces each of said plurality of third interconnections, and another side of each of said plurality of first interconnections faces each of said plurality of third interconnections,

an insulating layer is formed on said main surface and fills in between each of said plurality of first interconnections, between each of said plurality of third interconnections, and between one of said plurality of first interconnections and said plurality of third interconnections and said fifth interconnection adjacent to each other,

said plurality of first interconnections, said plurality of third interconnections, and said fifth interconnection are located to align at an equally pitch in a direction substantially perpendicular to said predetermined direction,

a capacitance is formed by said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection, and said insulating layer formed between each of said plurality of first interconnections and each of said plurality of third interconnections, and

said plurality of first interconnections and said second interconnection are one of electrodes of said capacitance, said plurality of third interconnections and said fourth interconnection are the other of said electrodes of said capacitance.

16. The semiconductor device according to claim 15 , wherein

a plurality of conductive films are formed in said predetermined region between said semiconductor substrate and said first plane.

17. The semiconductor device according to claim 16 , wherein

a plurality of active regions and a plurality of isolation regions are formed in said predetermined region in said semiconductor substrate, and

said plurality of conductive films are formed at least on said plurality of active regions or said plurality of isolation regions.

18. The semiconductor device according to claim 17 , wherein

in cross sectional view, each of said plurality of active regions and each of said plurality of isolation regions is arranged alternately to each other.

19. The semiconductor device according to claim 16 , wherein said conductive film is a polysilicon film.

20. The semiconductor device according to claim 15 , wherein

said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection, and said fifth interconnection are formed in a plurality of said first planes spaced apart from each other,

in plan view, each of said plurality of first interconnections in said first plane overlaps each of said plurality of third interconnections in said first plane adjacent to said first plane.

21. The semiconductor device according to claim 15 , wherein

said semiconductor substrate includes a first well layer of a first conductivity type extending in said main surface, said fifth interconnection electrically connected to said first well layer,

said first well layer being fixed at one of a ground potential or a power supply potential.

22. The semiconductor device according to claim 21 , wherein

said semiconductor substrate further includes a second well layer of a second conductivity type extending parallel to said first well layer at a position immediately below said predetermined region and apart from said main surface,

said second well layer being fixed at a potential different from the one of the ground potential or the power supply potential at which said first well layer is fixed.

23. The semiconductor device according to claim 15 , wherein

the fifth interconnection includes a plurality of fifth interconnections, and

said plurality of first interconnections and said plurality of third interconnections are formed between said plurality of fifth interconnections.

Assignments (9)