Memory controller having a plurality of memory regions for protection against power failure
A memory controller ( 1 ) writes data continuously to a first and a second blocks ( 20 A), ( 20 B) which are provided by dividing a memory region of a nonvolatile memory ( 2 ), and reads the data therefrom. The controller includes: a first writer ( 12 A) which writes data to the first block ( 20 A); and a second writer ( 12 B) which writes data to the second block ( 20 B) after completion of the writing by the first writer ( 12 A) and a lapse of a waiting time generally equal to a length of time necessary for a power breakdown to drop a power source voltage down to a voltage value to at least disable the writing of data to the memory region.
1. A memory controller for writing data continuously to a first and a second block provided by dividing a memory region of a nonvolatile memory, and for reading the data therefrom, comprising:
a first writer writing data to the first block of said memory while a power source voltage is maintained at a constant level;
a second writer writing the same data to the second block of said same memory as the data written to the first block, while the power source voltage is maintained at the constant level, after completion of the writing by the first writer and a lapse of a predetermined waiting time, the waiting time being longer than a period of time in which the power source voltage drops from a guaranteed writing level down to a disabled writing level disabling the writing of data to the memory region; and
a check code generator generating error detection check codes upon writing of data to each of the first and the second blocks, the first and the second writers writing the check codes to each of the first and the second blocks.
2. The memory controller according to claim 1 , further comprising: an error detector for detecting an error based on the stored data and the check codes, for each of the first and the second blocks upon reading the data from the memory region; and a reader for reading the data and the check codes from the first block and outputting the data read from the first block upon detection of no error by the error detector while reading the data and the check codes from the second block upon detection of an error and outputting the data read from the second block upon detection of no error by the error detector.
3. The memory controller according to claim 2 , wherein the reader outputs a stored default data if an error is found in both of the first and the second blocks.
4. The memory controller according to claim 1 , wherein the data stored in the memory region is binary data, the first writer writing the data as intact to the first block, the second writer writing to the second block a data obtained by inverting each of the binary values of the data written by the first writer to the first block.
5. The memory controller according to claim 4 , further comprising: an Exclusive OR (EOR) operator for calculating an EOR for a pair of mutually corresponding data stored in the first and the second blocks upon reading the data from the memory region; and a reader for reading the pair of mutually corresponding data from the first and the second blocks and outputting the data read from the first or the second block upon obtainment of a value 1 as a result of the EOR operation performed by the EOR operator.
6. The memory controller according to claim 5 , wherein the reader outputs a stored default data if a result of the EOR operation performed by the EOR operator is a value 0.
7. A memory controller for writing data continuously to a first and a second block provided by dividing a memory region of a nonvolatile memory, and for reading the data therefrom, comprising:
a first writer writing data to the first block while a power source voltage is maintained at a constant level;
a second writer writing the same data to the second block as the data written to the first block, while the power source voltage is maintained at the constant level, after completion of the writing by the first writer and a lapse of a predetermined waiting time, the waiting time being longer than a period of time in which the power source voltage drops from a guaranteed writing level down to a disabled writing level disabling the writing of data to the memory region; and
a check code generator for generating error detection check codes upon writing of data to each of the first and the second blocks, the first and the second writers writing the check codes to each of the first and the second blocks.
8. A memory controller for writing data continuously to a first and a second block provided by dividing a memory region of a nonvolatile memory, and for reading the data therefrom, comprising:
a first writer writing data to the first block while a power source voltage is maintained at a constant level; and
a second writer writing the same data to the second block as the data written to the first block, while the power source voltage is maintained at the constant level, after completion of the writing by the first writer and a lapse of a predetermined waiting time, the waiting time being longer than a period of time in which the power source voltage drops from a guaranteed writing level down to a disabled writing level disabling the writing of data to the memory region,
wherein the data stored in the memory region is binary data, the first writer writing the data as intact to the first block, the second writer writing to the second block a data obtained by inverting each of the binary values of the data written by the first writer to the first block.