IP Library Granted Patent US 7,952,099
Granted Patent B2
US 7,952,099 · App. 11/737,954 · Granted May 31, 2011

Thin film transistor liquid crystal display array substrate

Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.
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Quick Facts
Patent No.
US 7,952,099
App. No.
11/737,954
Granted
May 31, 2011
Kind
B2
Abstract

A TFT LCD array substrate and a manufacturing method thereof. The manufacturing method includes the steps of: forming a thin film transistor on a substrate to form a gate line and a gate electrode connected with the gate line on the substrate; forming a gate insulating layer and a semiconductor layer on the gate electrode; forming an ohmic contact layer on the semiconductor layer; forming a transparent pixel electrode layer and a source/drain electrode metal layer in sequence on the resultant substrate, wherein the transparent pixel electrode layer is electrically insulated from the gate line and the gate electrode, and the transparent pixel electrode layer forms an ohmic contact with two sides of the semiconductor layer via the ohmic contact layer; and performing masking and etching with a gray tone mask with respect to the resultant substrate to form a transparent pixel electrode, a source/drain electrode and a data line simultaneously.

Claims (20)

1. A TFT LCD array substrate, comprising:

a substrate and a pixel array on the substrate, each pixel comprising:

a gate line and a gate electrode connected with the gate line formed on the substrate;

a gate insulating layer formed on the gate electrode and a semiconductor layer formed on the gate insulating layer; and

an isolating dielectric layer covering the substrate, the gate line, the gate electrode, the gate insulating layer and the semiconductor layer, wherein via holes, in which an ohmic contact layer is deposited, are formed in the isolating dielectric layer over both sides of the semiconductor layer,

a transparent pixel electrode formed on the isolating dielectric layer and establishing an ohmic contact with the semiconductor layer via the ohmic contact layer in the via holes, and

a source electrode, a drain electrode and a data line, which are formed on the transparent pixel electrode.

2. The TFT LCD array substrate according to claim 1 , wherein the ohmic contact layer is a μc-Si layer.

3. The TFT LCD array substrate according to claim 1 , wherein the ohmic contact layer is a composite layer composed of a μc-Si material or n + a-Si layer and Mo, Cr, W, or alloy metal layers thereof.

4. The TFT LCD array substrate according to claim 1 , wherein the data line and drain electrode is integrated with each other.

5. A TFT LCD array substrate comprising a substrate and a pixel array on the substrate, each pixel comprising:

a thin film transistor formed on the substrate, wherein the thin film transistor includes a gate line and a gate electrode connected with the gate line formed on the substrate, a gate insulating layer formed on the gate electrode, a semiconductor layer, and an ohmic contact layer formed on at least two ends of the semiconductor layer;

a transparent pixel electrode formed on the thin film transistor, electrically insulated from the gate electrode and the gate line, and electrically contacted with the two ends of the semiconductor layer respectively via the ohmic contact layer;

a source/drain electrode and a data line formed on the transparent pixel electrode and electrically connected with the semiconductor layer via the transparent pixel electrode;

an isolation dielectric layer formed on the gate electrode, the gate line, the gate insulating layer and the semiconductor layer, wherein the transparent pixel electrode layer is insulated from the gate line and gate electrode via the isolating dielectric layer, and

via holes, in which an ohmic contact layer is deposited, formed on both sides of the isolating dielectric layer over the semiconductor layer.

6. The TFT LCD array substrate according to claim 5 , further comprising a passivation layer covering the transparent pixel electrode, the source/drain electrode and the data line.

7. The TFT LCD array substrate according to claim 5 , wherein the ohmic contact layer is a μc-Si layer.

8. The TFT LCD array substrate according to claim 5 , wherein the ohmic contact layer is a composite layer composed of a μc-Si material or n + a-Si layer and Mo, Cr, W, or alloy metal layers thereof.

9. The TFT LCD array substrate according to claim 5 , wherein the data line and drain electrode is integrated with each other.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015
From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD
To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD
Reel/Frame 036644/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2007
From: BOE TECHNOLOGY GROUP CO., LTD
To: BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 019985/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2007
From: DENG, CHAOYONG; RIM, SEUNG MOO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 019981/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2007
From: DENG, CHAOYONG; RIM, SEUNG MOO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 019198/0042 →
Priority Claims (2)
CN 2006 1 0074457 · Apr 21, 2006 · national
CN 2006 1 0080641 · May 23, 2006 · national
Continuity (1)
Related Publication 20070246707A1 · Oct 25, 2007