Method and system for routing in low density parity check (LDPC) decoders
An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.
1. A method comprising:
storing a first edge value in a first segment of memory; and
storing a second edge value in a second segment of memory, wherein the edge values are associated with a structured parity check matrix used to generate a low density parity check coded signal, the edge values specifying relationship of bit nodes and check nodes, wherein the first segment is contiguous with the second segment, and the first edge value and the second edge value are read during a single processor clock cycle for decoding the low density parity check coded signal.
2. A method according to claim 1 , wherein the memory is partitioned according to degrees of the bit nodes.
3. A method according to claim 2 , wherein edge values having bit nodes of n degrees are stored in a first portion of the memory, and edge values having bit nodes of greater than n degrees are stored in a second portion of the memory, n being an integer.
4. A method according to claim 1 , wherein addresses of the memory is stored in a Read-Only memory.
5. A method according to claim 1 , wherein M bit nodes or M check nodes correspond to the edge values, and M parallel processing engines are utilized to decode the low density parity check coded signal.
6. A computer-readable storage medium bearing instructions that are arranged, upon execution, to cause one or more processors to perform the method of claim 1 .
7. A memory device comprising:
a first segment configured to store a first edge value; and
a second segment contiguous with the first segment and configured to store a second edge value, wherein the edge values are associated with a structured parity check matrix used to generate a low density parity check coded signal, the edge values specifying relationship of bit nodes and check nodes, wherein the first edge value and the second edge value are read during a single processor clock cycle for decoding the low density parity check coded signal.
8. A device according to claim 7 , wherein the memory is partitioned according to degrees of the bit nodes.
9. A device according to claim 8 , wherein edge values having bit nodes of n degrees are stored in a first portion of the memory, and
edge values having bit nodes of greater than n degrees are stored in a second portion of the memory, n being an integer.
10. A device according to claim 7 , wherein addresses of the memory is stored in a Read-Only memory.
11. A device according to claim 7 , wherein M bit nodes or M check nodes correspond to the edge values, and M parallel processing engines are utilized to decode the low density parity check coded signal.
12. A system comprising:
a memory including,
a first segment configured to store a first edge value, and
a second segment contiguous with the first segment and configured to store a second edge value, wherein the edge values are associated with a structured parity check
matrix used to generate a low density parity check coded signal, the edge values specifying relationship of bit nodes and check nodes; and
a plurality of processing engines configured to read the edge values during a single clock cycle for decoding the low density parity check coded signal.
13. A system according to claim 12 , wherein the memory is partitioned according to degrees of the bit nodes.
14. A system according to claim 13 , wherein edge values having bit nodes of n degrees are stored in a first portion of the memory, and edge values having bit nodes of greater than n degrees are stored in a second portion of the memory, n being an integer.
15. A system according to claim 12 , wherein addresses of the memory is stored in a Read-Only memory.
16. A method comprising:
reading, during a single processor clock cycle, a first edge value stored in a first segment of memory; and
reading, during the single processor clock cycle, a second edge value in a second segment of memory, wherein the edge values are associated with a structured parity check matrix used to generate a low density parity check coded signal, the edge values specifying relationship of bit nodes and check nodes, wherein the first segment is contiguous with the second segment for decoding the low density parity check coded signal.
17. A method according to claim 16 , wherein the memory is partitioned according to degrees of the bit nodes.
18. A method according to claim 17 , wherein edge values having bit nodes of n degrees are stored in a first portion of the memory, and edge values having bit nodes of greater than n degrees are stored in a second portion of the memory, n being an integer.
19. A method according to claim 16 , wherein addresses of the memory is stored in a Read-Only memory.
20. A method according to claim 16 , wherein M bit nodes or M check nodes correspond to the edge values, and M parallel processing engines are utilized to decode the low density parity check coded signal.
21. A computer-readable storage medium bearing instructions that are arranged, upon execution, to cause one or more processors to perform the method of claim 16 .