Processor arrays made of standard memory cells
Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).
1. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising:
a plurality of memory cells interconnected by a plurality of bit lines and
a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein each of the stored vectors is stored in said memory cells along one of said bit lines, the input vector is introduced by activating a selected set of word lines of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines; and where the circuit also performs standard memory functions.
2. The circuit of claim 1 , wherein said memory cells are standard SRAM cells.
3. The circuit of claim 1 , wherein said memory cells are standard DRAM cells.
4. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising:
a plurality of memory cells interconnected by a plurality of bit lines and
a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein each of the stored vectors is stored in said memory cells along one of said bit lines, the input vector is introduced by activating a selected set of word lines of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines; and where the circuit also performs standard memory functions,
wherein said SRAM cells comprise pull-down devices and said sense amplifier comprises voltage limiting sub-circuits which force the voltage on said bit lines to a level not lower than a threshold voltage, which is higher than the threshold voltage of said pull-down devices.
5. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising:
a plurality of memory cells interconnected by a plurality of bit lines and
a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein each of the stored vectors is stored in said memory cells along one of said bit lines, the input vector is introduced by activating a selected set of word lines of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines;
and where the circuit also performs standard memory functions,
wherein a portion of said bit lines are inverted bit lines, wherein a sum of product operation is executed in parallel for the stored vectors and the inverse of the stored vectors, the sum-of-products operation of an input vector and the stored vectors being performed by said sense amplifier sensing a voltage level on said bit lines, and the sum-of-products operation of an input vector and the inverse of the stored vectors being performed by said sense amplifier measuring a voltage level on said inverted bit lines.
6. A circuit to concurrently evaluate sum-of-products function of a given input vector and a multitude of stored vectors, comprising a standard DRAM array, where stored vectors are stored along bit lines in DRAM cells in said DRAM array, input vectors are introduced by activating selected Read-Write lines of said DRAM array, and sum-of-products are evaluated by sensing the voltage level on said bit lines; and where said DRAM array also retains standard DRAM functionality.
7. The circuit of claim 6 , wherein the sum-of-products operation is destructive.
8. The circuit of claim 6 , wherein separate products are read sequentially, in parallel for a multitude of stored vectors, and with logic external to said array determining the logic level of a sum of the products.