Semiconductor device and fabrication method thereof

1. A fabrication method of a semiconductor device, comprising the steps of:

providing a semiconductor chip having an inner circuit and a plurality of connection bumps electrically connected to the inner circuit, and a substrate having a plurality of circuit layers formed thereon by wet etching and a plurality of solder pads formed by wet etching a conductive metal layer for being electrically connected to the connection bumps;

flipping the semiconductor chip to enable the connection bumps to correspond to the solder pads in position; and

compressing the substrate and the semiconductor chip toward each other at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, such that the solder pads are embedded into the connection bumps,

wherein the substrate is formed by wet etching a surface of a core board so as to form the solder pads on the surface of the core board, and

a top surface of each of the circuit layers is smaller in area than a bottom surface of each of the circuit layers.

2. The fabrication method of claim 1 , wherein each of the solder pads has a cross section in a convex shape.

3. The fabrication method of claim 1 , wherein a top surface of each of the solder pads is smaller in area than a bottom surface of each of the solder pads.

4. The fabrication method of claim 1 , wherein a cross section of each of the solder pads is in a shape selected from the group consisting of cone, triangle, trapezoid and warhead.

5. The fabrication method of claim 1 , wherein each of the connection bumps has a first contact end, and each of the solder pads has a second contact end correspondingly connected to the first contact end and narrower than the first contact end in width.

6. The fabrication method of claim 1 , wherein a cross section of each of the circuit layers is in a shape selected from the group consisting of cone, triangle, trapezoid, and warhead.

7. The fabrication method of claim 1 , wherein the connection bumps of the semiconductor chip and the solder pads of the substrate are compressed by a thermal compression or thermal sonic compression process.

8. The fabrication method of claim 1 , wherein the temperature of the compression between the connection bumps and the solder pads ranges from 50° C. to 180° C.

9. The fabrication method of claim 1 , wherein the connection bumps are lower in rigidity than the solder pads on the substrate.

10. The fabrication method of claim 9 , wherein the connection bumps are metal bumps made of solder tin or gold.

11. The fabrication method of claim 9 , wherein the solder pads are made of a metallic material selected from the group consisting of copper, nickel, and nickel-copper alloy.

12. The fabrication method of claim 1 , wherein a flip-chip underfill material is filled between the semiconductor chip and the substrate.

13. The fabrication method of claim 1 , wherein the formation of the substrate comprises the steps of:

forming the conductive metal layer on a core board;

forming on the conductive metal layer a photoresist layer having a plurality of openings for exposing a portion of the conductive metal layer; and

removing the conductive metal layer exposed from the openings by using an etching solution, followed by removing the photoresist layer, so as to form the solder pads on the core board to thereby allow the core board and solder pads thereon together to form the substrate.

14. The fabrication method of claim 13 , wherein top surfaces of the solder pads are smaller in area than bottom surfaces of the solder pads.