Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide

1. A memory cell comprising:

a floating gate NMOS transistor including a source that forms a first terminal of the memory cell, a drain, and a gate;

a high voltage PMOS transistor including a source, an extended drain connected to the drain of the floating gate transistor, and a gate forming a second terminal of the memory cell; and

a capacitor including a first terminal connected to the gate of the floating gate transistor, and a second terminal forming a third terminal of the memory cell;

wherein the floating gate transistor can store a logic state; and

wherein combinations of voltages can be applied to the first, second, and third terminals of the memory cell to program, inhibit program, read, and erase the logic state stored by the floating gate transistor;

wherein to program the cell a program voltage is applied to the first terminal, and a select voltage is applied to the second and third terminals;

to inhibit programming of the cell the second terminal is connected to ground;

to read the cell a read voltage is applied to the first terminal, a select voltage is applied to the second terminal, and the third terminal is connected to ground; and

to erase the cell an erase voltage is applied to the first terminal, and the second and third terminals are connected to ground.

2. The memory cell of claim 1 , wherein the erase voltage is at least twice the program voltage.

3. The memory cell of claim 1 , wherein:

the program voltage is about 5-10 volts;

the read voltage is about 1 volt; and

the erase voltage is about 14-20 volts.

4. A method for operating a memory cell that comprises:

a floating gate transistor including a source that forms a first terminal of the memory cell, a drain, and a gate;

a high voltage transistor including a source, an extended drain connected to the drain of the floating gate transistor, and a gate forming a second terminal of the memory cell; and

a capacitor including a first terminal connected to the gate of the floating gate transistor, and a second terminal forming a third terminal of the memory cell;

the method comprising:

programming the memory cell by applying a program voltage to the first terminal of the memory cell and a select voltage to the second and third terminals of the memory cell;

inhibiting programming of the memory cell by connecting the second terminal of the memory cell to ground;

reading the memory cell by applying a read voltage to the first terminal of the memory cell, applying a select voltage to the second terminal of the memory cell, and connecting the third terminal to ground; and

erasing the memory cell by applying an erase voltage to the first terminal of the memory cell and connecting the second and third terminals of the memory cell to ground.

5. The method claim 4 , wherein the source of the high voltage transistor is connected to ground.

6. The method of claim 4 , wherein the erase voltage is at least twice the program voltage.

7. The method of claim 4 , wherein:

the program voltage is about 5-10 volts;

the read voltage is about 1 volt; and

the erase voltage is about 14-20 volts.

8. The memory cell of claim 1 , wherein the source of the high voltage transistor is connected to ground.

9. The memory cell of claim 1 , wherein the gate of the floating gate transistor is on a gate oxide layer having a thickness in the range of about 10 nm to about 15 nm.

10. The memory cell of claim 1 , wherein the gate of the floating gate transistor is on a gate oxide layer having a thickness of at least 12 nm.

11. The memory cell of claim 1 , wherein:

the gate of the floating gate NMOS transistor is unsilicided; and

the capacitor includes a gate that is unsilicided.

12. The memory cell of claim 1 , wherein:

the gate of the floating gate NMOS transistor is unsilicided; and

the capacitor includes a gate that is silicided.