Radio frequency transceiver front end circuit with matching circuit voltage divider
A front end circuit for coupling an antenna to a radio frequency (RF) transceiver for time domain duplex systems is disclosed. The front end circuit includes an antenna port, a power amplifier, a low noise amplifier, and a matching network. The output of the power amplifier and the input of the low noise amplifier are coupled to the matching network and connected in common to the antenna. The power amplifier and the low noise amplifier are activated and deactivated in sequence corresponding to the transmit and receive modes of the transceiver, and the matching network minimizes the effect that one has on the other at the designated operating frequency.
1. A radio frequency (RF) transceiver front end circuit with a predefined operating frequency for connecting a transceiver to an antenna, the front end circuit comprising:
an antenna port connectable to the antenna;
a transmit port;
a receive port;
a power amplifier including a first power amplifier transistor having a base coupled to the transmit port, a collector, and an emitter;
a low noise amplifier coupled to the transmit port including a first low noise amplifier transistor having a base, a collector, and an emitter;
a matching circuit including a power amplifier output matching segment coupled to the collector of the first power amplifier transistor and the antenna port, and a low noise amplifier input matching segment coupled to the base of the first low noise amplifier transistor and the antenna port, the power amplifier matching segment having shared components with the low noise amplifier segment; and
an intermediate junction coupling the low noise amplifier input matching segment and the power amplifier output matching segment including a voltage divider network.
2. The front end circuit of claim 1 , wherein the power amplifier output matching segment includes a first inductor coupled to the collector of the first power amplifier transistor.
3. The front end circuit of claim 2 , wherein the power amplifier output matching segment include a second inductor connected in series to the first inductor, the connection between the first inductor and the second inductor defining the intermediate junction.
4. The front end circuit of claim 3 , wherein the first inductor is excluded from a receive chain of the low noise amplifier input matching segment.
5. The front end circuit of claim 2 , wherein the power amplifier output matching segment includes a second inductor and a third inductor connected in series between a power amplifier collector bias source and the first inductor.
6. The front end circuit of claim 5 , wherein a point between the second inductor and the third inductor defines the intermediate junction.
7. The front end circuit of claim 6 , wherein the first inductor and the third inductor is excluded from a signal chain of the low noise amplifier input matching segment.
8. The front end circuit of claim 1 , wherein components of the low noise amplifier matching segment correspond to a substantially minimized noise figure between the antenna port and the low noise amplifier signal output.
9. The front end circuit of claim 1 , wherein components of the second network segment correspond to a substantially minimized voltage swing at the base of the low noise amplifier transistor.
10. The front end circuit of claim 1 , wherein the low noise amplifier matching segment includes a first capacitor and a first inductor in a series chain coupled to the base of the low noise amplifier transistor and the intermediate junction.
11. The front end circuit of claim 1 , wherein the power amplifier has a plurality of amplification stages including a plurality of interconnected power amplifier transistors.
12. The front end circuit of claim 1 , wherein the low noise amplifier has a plurality of amplification stages including a plurality of interconnected low noise amplifier transistors.
13. The front end circuit of claim 1 , wherein the first power amplifier transistor and the first low noise amplifier transistor has a transistor structure selected from the group consisting of: bipolar junction and hetero-junction bipolar.
14. The front end circuit of claim 1 , wherein:
the first power amplifier transistor and the first low noise amplifier transistor has a transistor structure selected from the group consisting of: metal semiconductor field effect, metal oxide semiconductor field effect, and high electron mobility;
the respective one of the collectors of the first low noise amplifier transistor and the first power amplifier transistor corresponding to drains;
the respective one of the emitters of the first low noise amplifier transistor and the first power amplifier transistor corresponding to sources; and
the respective one of the bases of the first low noise amplifier transistor and the first power amplifier transistor corresponding to gates.