Atomic operation on non-standard sized data using external cache

1. In a processor system comprising a main memory and a first processor element including a first processor unit coupled to an external cache, a method for atomic operation, the method for executing an atomic operation instruction, the method comprising:

a) when executing the atomic operation instruction with the first processor unit, atomically loading data from a lock-line in the main memory into a first location X in the external cache, wherein a size of the data is larger than a data size for standard atomic operations with the first processor unit, wherein the lock-line is accessible by the first processor unit and a second processor unit in a lock-free manner, wherein the first and second processor units have different reservation sizes for atomic operations, wherein a data size for the lock-line is larger than a reservation size for standard atomic operations with the first processor unit; and

b) when executing the atomic operation instruction reserving the data in a second location Y in the external cache, wherein reserving the data in the second location includes

copying the contents of the first location X into the second location Y; and

making an indication that the contents of the second location Y have been changed subsequent to a prior reservation.

2. The method of claim 1 , wherein a data size of the lock-line is as large as or larger than a reservation size for atomic operations performed by the second processor unit.

3. The method of claim 2 wherein the data size of the lock line is 128 bytes.

4. The method of claim 2 , further comprising, storing data to the lock-line with the second processor unit.

5. The method of claim 4 , wherein the second processor unit stores data to the lock-line prior to a).

6. The method of claim 4 wherein a data size of the lock-line is as large as a data size for atomic operations that may be performed by the second processor unit.

7. The method of claim 4 wherein the data size of the lock line is 128 bytes.

8. The method of claim 7 wherein the data size for the standard atomic operations that may be performed with the first processor unit is 8 bytes.

9. The method of claim 1 , further comprising:

with the first processor unit, storing data loaded into the second location Y back to the lock-line if a previous reservation of the data in location Y by the first processor unit has not been lost.

10. The method of claim 1 wherein a) and b) are performed by a thread running on the first processor unit.

11. The method of claim 10 wherein b) includes:

copying the contents of the first location X into the second location Y; and

making an indication that the contents of the second location Y have been changed subsequent to a prior reservation by a different thread.

12. The method of claim 11 , wherein the different thread is a thread running on the second processor unit.

13. A processor system, comprising:

a main memory;

a first processor element coupled to the main memory, wherein the first processor element includes a first processor unit coupled to an external cache, wherein the first processor element has embodied therein a processor executable instruction that, when executed by the first processor element, implement a method for atomic operation, the instruction comprising:

a) atomically loading data from a lock-line in the main memory into a first location X in the external cache, wherein a size of the data is larger than a data size for standard atomic operations that may be performed with the first processor unit, wherein the lock-line is accessible by the first processor unit and a second processor unit in a lock-free manner, wherein the first and second processor units have different reservation sizes for atomic operations, wherein a data size for the lock-line is larger than a reservation size for standard atomic operations with the first processor element; and

b) reserve the data in a second location Y in the external cache, wherein reserving the data in the second location includes copying the contents of the first location X into the second location Y; and making an indication that the contents of the second location Y have been changed subsequent to a prior reservation.

14. The system of claim 13 , further comprising one or more second processor elements coupled to the first processor unit.

15. The system of claim 14 wherein a data size of the lock-line is as large as or larger than a data size for atomic operations that may be performed by the second processor units.

16. The system of claim 15 wherein the data size of the lock line is 128 bytes.

17. The system of claim 15 , wherein one or more of the second processor units include instructions that, when executed by the one or more second processor units, store data to the lock-line.

18. The system of claim 17 wherein the data size of the lock line is 128 bytes.

19. The system of claim 18 wherein the data size for the standard atomic operations that may be performed with the first processor unit is 8 bytes.

20. The system of claim 13 wherein the first processor unit further has embodied therein processor executable instructions that, when executed by the first processor unit store data loaded into the second location Y back to the lock-line if a previous reservation of the data in location Y by the first processor unit has not been lost.

21. The system of claim 13 wherein main memory has embodied therein a program comprising one or more threads, wherein one or more of the threads includes command for the instructions a) and b) to be executed by the first processor unit.

22. The system of claim 21 wherein b) includes:

an instruction that, when executed by the first processor unit, copies the contents of the first location X into the second location Y; and

an instruction that, when executed by the first processor unit, makes an indication that the contents of the second location Y have been changed subsequent to a prior reservation by a different thread.

23. A non-transitory processor readable medium having embodied therein a processor executable instruction configured to implement a method for atomic operation on a processor system comprising a main memory and a first processor element, wherein the first processor element includes a first processor unit and an external cache, the instruction comprising:

a) atomically loading data from a lock-line in the main memory into a first location X in the external cache, wherein a size of the data is larger than a data size for standard atomic operations that may be performed with the first processor unit, wherein the lock-line is accessible by the first processor unit and a second processor unit in a lock-free manner, wherein the first and second processor units have different reservation sizes for atomic operations, wherein a data size for the lock-line is larger than a reservation size for standard atomic operations with the first processor element; and

b) reserving the data in a second location Y in the external cache, wherein reserving the data in the second location includes copying the contents of the first location X into the second location Y; and making an indication that the contents of the second location Y have been changed subsequent to a prior reservation.