Semiconductor device and structure
View Patent ↗A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.
1. A device comprising semiconductor memories, the device comprising: a first monocrystalline silicon transferred layer; a second monocrystalline silicon transferred layer; wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors; wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors; and wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.
2. A device according to claim 1 , further comprising: a plurality of a memory cell control lines embedded within said first monocrystalline silicon transferred layer and said second monocrystalline silicon transferred layer.
3. A device according to claim 1 , wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.
4. A device according to claim 1 , wherein said semiconductor memories are dynamic random access memory (DRAM) type memory.
5. A device according to claim 1 , wherein said semiconductor memories are charge-trap type memory.
6. A device according to claim 1 , wherein said semiconductor memories are floating-gate type memory.
7. A device according to claim 1 , wherein said semiconductor memories are resistive-random-access memory (RAM) type memory.
8. A device according to claim 1 , wherein said semiconductor memories are phase-change type memory.
9. A device comprising semiconductor memories, the device comprising: a first monocrystalline silicon transferred layer; a second monocrystalline silicon transferred layer, wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors; wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors; wherein said first monocrystalline silicon transferred layer further comprises a first plurality of select lines as memory cell control lines, and wherein said second monocrystalline silicon transferred layer further comprises a second plurality of select lines as memory cell control lines.
10. A device according to claim 9 , wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.
11. A device according to claim 9 , wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.
12. A device according to claim 9 , wherein said semiconductor memories are DRAM type memory.
13. A device according to claim 9 wherein said semiconductor memories are resistive-RAM type memory.
14. A device according to claim 9 , wherein said semiconductor memories are phase-change type memory.
15. A device comprising semiconductor memories, said device comprising: a first monocrystalline silicon transferred layer; a second monocrystalline silicon transferred layer, wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors; wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors; wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.
16. A device according to claim 15 , further comprising:
a plurality of a memory cell control lines embedded within said first layer and said second layer.
17. A device according to claim 15 , wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.
18. A device according to claim 15 , wherein said semiconductor memories are DRAM type memory.
19. A device according to claim 15 , wherein said semiconductor memories are resistive-RAM type memory.
20. A device according to claim 15 , wherein said semiconductor memories are phase-change type memory.