Frequency multiplier
In one aspect, the present invention provides a frequency multiplier. In some embodiments, the frequency multiplier includes: a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to a third terminal of the second transistor through a first capacitor, and a first terminal of the second transistor is connected to a third terminal of the first transistor through a second capacitor. The frequency multiplier may also include a balun, wherein the third terminal of the first transistor is connected to a terminal of the balun, and the third terminal of the second transistor is connected to a different terminal of the balun.
1. A frequency multiplier, comprising:
a first transistor (Q 1 ) having a first terminal, a second terminal and a third terminal;
a second transistor (Q 2 ) having a first terminal, a second terminal and a third terminal;
a voltage controlled oscillator (VCO) and
a balun comprising a first balanced terminal, a second balanced terminal and a third terminal, wherein
the first terminal of the first transistor is connected to the third terminal of the second transistor through one or more circuit elements, said one or more circuit elements including a first capacitor,
the first terminal of the second transistor is connected to the third terminal of the first transistor through one or more circuit elements, said one or more circuit elements including a second capacitor,
the third terminal of the first transistor is connected to the first balanced terminal of the balun,
the third terminal of the second transistor is connected to the second balanced terminal of the balun,
the second terminal of the first transistor is connected to an output node,
the second terminal of the second transistor is connected to the same output node, and
the vco is connected to the third terminal of the balun.
2. The frequency multiplier of claim 1 , wherein the first transistor is a bipolar junction transistor (BJT) and the second transistor is a BJT, and wherein
the first terminal of the first transistor is the base of the first transistor,
the first terminal of the second transistor is the base of the second transistor,
the second terminal of the first transistor is the collector of the first transistor,
the second terminal of the second transistor is the collector of the second transistor,
the third terminal of the first transistor is the emitter of the first transistor, and
the third terminal of the second transistor is the emitter of the second transistor.
3. The frequency multiplier of claim 1 , wherein the first transistor is a field effect transistor and the second transistor is a field effect transistor, and wherein
the first terminal of the first transistor is the gate of the first transistor,
the first terminal of the second transistor is the gate of the second transistor,
the second terminal of the first transistor is the drain of the first transistor,
the second terminal of the second transistor is the drain of the second transistor,
the third terminal of the first transistor is the source of the first transistor, and
the third terminal of the second transistor is the source of the second transistor.
4. The frequency multiplier of claim 1 , further comprising a third capacitor, wherein the third terminal of the first transistor is connected to the third terminal of the second transistor through the third capacitor.
5. The frequency multiplier of claim 1 , wherein the first terminal of the first transistor and the first terminal of the second transistor are biased at a turn-on voltage.
6. A high frequency transceiver comprising the frequency multiplier according to claim 1 .
7. A high frequency radar system comprising the frequency multiplier according to claim 1 .
8. A high frequency radar system comprising the frequency multiplier according to claim 1 .
9. A frequency multiplier, comprising:
a first transistor (Q 1 ) having a first terminal, a second terminal and a third terminal;
a second transistor (Q 2 ) having a first terminal, a second terminal and a third terminal;
a balun;
a first capacitor;
a second capacitor; and
a third capacitor, wherein
the first terminal of the first transistor is connected to the third terminal of the second transistor through one or more circuit elements, said one or more circuit elements including the first capacitor,
the first terminal of the second transistor is connected to the third terminal of the first transistor through one or more circuit elements, said one or more circuit elements including the second capacitor,
the third terminal of the first transistor is connected to a first terminal of the balun,
the third terminal of the second transistor is connected to a second terminal of the balun,
the second terminal of the first transistor is connected to an output node,
the second terminal of the second transistor is connected to the same output node,
the third terminal of the first transistor is not directly connected to the third terminal of the second transistor, and
the third terminal of the first transistor is connected to the third terminal of the second transistor through the third capacitor.
10. The frequency multiplier of claim 9 , wherein the first transistor is a bipolar junction transistor (BJT) and the second transistor is a BJT, and wherein
the first terminal of the first transistor is the base of the first transistor,
the first terminal of the second transistor is the base of the second transistor,
the second terminal of the first transistor is the collector of the first transistor,
the second terminal of the second transistor is the collector of the second transistor,
the third terminal of the first transistor is the emitter of the first transistor, and
the third terminal of the second transistor is the emitter of the second transistor.
11. The frequency multiplier of claim 9 , wherein the first transistor is a field effect transistor and the second transistor is a field effect transistor, and wherein
the first terminal of the first transistor is the gate of the first transistor,
the first terminal of the second transistor is the gate of the second transistor,
the second terminal of the first transistor is the drain of the first transistor,
the second terminal of the second transistor is the drain of the second transistor,
the third terminal of the first transistor is the source of the first transistor, and
the third terminal of the second transistor is the source of the second transistor.
12. The frequency multiplier of claim 9 , wherein the first terminal of the first transistor and the first terminal of the second transistor are biased at a turn-on voltage.
13. A high frequency transceiver comprising the frequency multiplier according to claim 9 .