Transmitter/receiver device that converts serial and parallel signals and method of testing thereof
A transmitter/receiver device includes: a transmitter unit including a parallel/serial converting circuit, a waveform deteriorating circuit, and a transmitter circuit; and a receiver unit including a receiver circuit, a serial/parallel converting circuit, and an error detecting circuit. The parallel/serial converting circuit converts a transmitter-side parallel signal to a transmitter-side serial signal. The waveform deteriorating circuit deteriorates a signal waveform of the transmitter-side serial signal. The transmitter circuit transmits to the receiver unit the signal whose waveform is deteriorated. The receiver circuit receives, as a receiver-side serial signal, the signal transmitted from the transmitter circuit. The serial/parallel converting circuit converts the receiver-side serial signal to a receiver-side parallel signal. The error detecting circuit detects a bit error rate of the receiver-side parallel signal.
1. A transmitter/receiver device having a transmitter unit and a receiver unit, wherein:
said transmitter unit comprises:
a parallel/serial converting circuit converting a transmitter-side parallel signal to a transmitter-side serial signal;
a pre-emphasis circuit deteriorating a signal waveform of said transmitter-side serial signal by an amplitude attenuation function which attenuates a signal amplitude of said transmitter-side serial signal by utilizing a pre-emphasis function which emphasizes a high-frequency component of said transmitter-side serial signal; and
a transmitter circuit transmitting to said receiver unit the signal which waveform is deteriorated by the amplitude attenuation function of said pre-emphasis circuit; and
said receiving unit comprises:
a receiver circuit receiving, as a receiver-side serial signal, the signal transmitted from said transmitter circuit;
a serial/parallel converting circuit converting said receiver-side serial signal to a receiver-side parallel signal; and
an error detecting circuit detecting a bit error rate of said receiver-side parallel signal.
2. The transmitter/receiver device according to claim 1 , further comprising
a variable filter which filters said transmitter-side serial signal based on a frequency characteristic, the frequency characteristic being set according to a loss characteristic of a transmission medium.
3. The transmitter/receiver device according to claim 1 , further comprising
a duty cycle distortion generating circuit which generates duty cycle distortion in said transmitter-side serial signal.
4. The transmitter/receiver device according to claim 1 , further comprising:
a clock generating circuit which generates, based on a reference clock, a clock used in a conversion operation of said parallel/serial converting circuit; and
a sinusoidal jitter generating circuit which generates sinusoidal jitter in said reference clock.
5. The transmitter/receiver device according to claim 1 , further comprising:
a clock generating circuit which generates, based on a reference clock, a clock used in a conversion operation of said parallel/serial converting circuit; and
a white noise generating circuit which generates white noise in said reference clock.
6. The transmitter/receiver device according to claim 1 , further comprising:
a clock generating circuit which generates, based on a reference clock, a clock used in a conversion operation of said parallel/serial converting circuit; and
a jitter generating circuit which selects one of sinusoidal jitter or white noise and generates the selected one in said reference clock.
7. The transmitter/receiver device according to claim 1 , further comprising:
an equalizing circuit which deteriorates a signal waveform of said receiver-side serial signal by an amplitude attenuation function which attenuates a signal amplitude of said receiver-side serial signal by utilizing an equalizing function which emphasizes a high-frequency component of said receiver-side serial signal, wherein
said serial/parallel converting circuit converts the signal whose waveform is deteriorated by the amplitude attenuation function of said equalizing circuit to said receiver-side parallel signal.
8. The transmitter/receiver device according to claim 7 , further comprising:
a signal path which is set for supplying the signal whose waveform is deteriorated by the amplitude attenuation function of said equalizing circuit to said transmitter circuit and which becomes effective when receiving a signal transmitted from an external part as said receiver-side serial signal, wherein
said transmitter circuit transmits the signal whose waveform is deteriorated by the amplitude attenuation function of said equalizing circuit to an external part when said signal path becomes effective.
9. A transmitter/receiver device having a transmitter unit and a receiver unit, wherein:
said transmitter unit comprises:
a parallel/serial converting circuit converting a transmitter-side parallel signal to a transmitter-side serial signal; and
a transmitter circuit transmitting said transmitter-side serial signal to said receiving unit; and
said receiver unit comprises:
a receiver circuit receiving, as a receiver-side serial signal, the signal transmitted from said transmitter circuit;
an equalizing circuit deteriorating a signal waveform of said receiver-side serial signal by an amplitude attenuation function which attenuates a signal amplitude of said receiver-side serial signal by utilizing an equalizing function which emphasizes a high-frequency component of said receiver-side serial signal;
a serial/parallel converting circuit converting the signal whose waveform is deteriorated by the amplitude attenuation function of said equalizing circuit to a receiver-side parallel signal; and
an error detecting circuit detecting a bit error rate of said receiver-side parallel signal.
10. The transmitter/receiver device according to claim 9 , further comprising
a duty cycle distortion generating circuit which generates duty cycle distortion in said receiver-side serial signal.
11. The transmitter/receiver device according to claim 9 , further comprising
a sinusoidal jitter generating circuit which generates sinusoidal jitter in said receiver-side serial signal.
12. The transmitter/receiver device according to claim 9 , further comprising
a white noise generating circuit which generates white noise in said receiver-side serial signal.
13. The transmitter/receiver device according to claim 9 , further comprising
a jitter generating circuit which selects one of sinusoidal jitter and white noise and generates the selected one in said receiver-side serial signal.
14. A method of testing a transmitter/receiver device having a transmitter unit and a receiver unit, the method comprising:
executing in said transmitter unit:
converting a transmitter-side parallel signal to a transmitter-side serial signal;
deteriorating a signal waveform of said transmitter-side serial signal by an amplitude attenuation function which attenuates a signal amplitude of said transmitter-side serial signal by utilizing a pre-emphasis function which emphasizes a high-frequency component of said transmitter-side serial signal; and
transmitting the signal whose waveform is deteriorated by the amplitude attenuation function, and
executing in said receiver unit:
receiving, as a receiver-side serial signal, said signal whose waveform is deteriorated;
converting said receiver-side serial signal to a receiver-side parallel signal; and
detecting a bit error rate of said receiver-side parallel signal to measure a signal transmission margin.
15. The method of testing the transmitter/receiver device according to claim 14 , further comprising
filtering said transmitter-side serial signal based on a frequency characteristic set according to a loss characteristic of a transmission medium.
16. The method of testing the transmitter/receiver device according to claim 14 , further comprising
generating duty cycle distortion in said transmitter-side serial signal.
17. The method of testing the transmitter/receiver device according to claim 14 , further comprising:
generating, based on a reference clock, a clock used in converting said transmitter-side parallel signal to said transmitter-side serial signal; and
generating sinusoidal jitter in said reference clock.
18. The method of testing the transmitter/receiver device according to claim 14 , further comprising:
generating, based on a reference clock, a clock used in converting said transmitter-side parallel signal to said transmitter-side serial signal; and
generating white noise in said reference clock.
19. The method of testing the transmitter/receiver device according to claim 14 , further comprising:
generating, based on a reference clock, a clock used in converting said transmitter-side parallel signal to said transmitter-side serial signal; and
selecting one of sinusoidal jitter and white noise and generating the selected one in said reference clock.
20. The method of testing the transmitter/receiver device according to claim 14 , wherein
deteriorating the signal waveform of said transmitter-side serial signal, an eye opening width of said transmitter-side serial signal is adjusted to an eye opening width prescribed in a predetermined standard.