IP Library Granted Patent US 8,072,044
Granted Patent B2
US 8,072,044 · App. 12/561,988 · Granted Dec 6, 2011

Semiconductor die containing lateral edge shapes and textures

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,072,044
App. No.
12/561,988
Granted
Dec 6, 2011
Kind
B2
Abstract

Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

Claims (35)

1. A semiconductor die containing an integrated circuit, comprising:

an upper semiconductor material surface;

a semiconductor bottom surface having an area smaller than the upper surface by about 1 to 75%;

a sidewall between the upper and bottom surfaces that is not perpendicular to the upper or bottom surface; and

a backside layer on the bottom surface.

2. The die of claim 1 , wherein the area of the smaller surface is smaller than the area of the upper surface by about 5 to about 50%.

3. The die of claim 1 , wherein the angle of the sidewall is greater than 0 but less than about 65 degrees relative to a vertical plane that is substantially perpendicular to the upper or bottom surface.

4. The die of claim 3 , wherein the sidewall angle ranges from about 10 to about 25 degrees.

5. The die of claim 4 , wherein the sidewall angle ranges from about 10 to about 15 degrees.

6. The die of claim 1 , wherein the sidewall comprises a concave shape near the bottom surface of the die and a straight shape near the upper surface.

7. The die of claim 1 , wherein the sidewall contains both a rough portion and a smooth portion.

8. The die of claim 7 , wherein the rough portion of the sidewall extends from about 5 to about 250 μm from the bottom surface.

9. The die of claim 8 , wherein the rough portion comprises from about 10 to about 90% of the sidewall and the smooth portion comprises about 90 to about 10%.

10. The die of claim 1 , wherein the die is connected to a leadframe.

11. A semiconductor die containing an integrated circuit, comprising:

an upper surface;

a bottom surface having an area smaller than the upper surface by about 1 to about 75%; and

a backside layer formed on the bottom surface;

a sidewall between the upper and bottom surfaces that is not perpendicular to the upper or bottom surface and that contains both a rough portion near the bottom surface and a smooth portion near the upper surface.

12. The die of claim 3 , wherein the angle of the sidewall angle ranges from about 10 to about 25 degrees relative to a vertical plane that is substantially perpendicular to the upper or bottom surface.

13. The die of claim 12 , wherein the sidewall angle ranges from about 10 to about 15 degrees.

14. The die of claim 11 , wherein the sidewall comprises a concave shape near the bottom surface of the die and a straight shape near the upper surface.

15. The die of claim 14 , wherein the curved slope of the concave shape extends from about 10 to about 200 μm from the bottom surface.

16. The die of claim 11 , wherein the rough portion of the sidewall extends from about 5 to about 250 μm from the bottom surface.

17. The die of claim 16 , wherein the rough portion comprises from about 10 to about 90% of the sidewall and the smooth portion comprises about 90 to about 10%.

18. An electronic device containing a semiconductor die with an integrated circuit, the die comprising:

an upper surface;

a bottom surface having an area smaller than the upper surface by about 1 to about 75%; and

a backside layer formed on the bottom surface;

a sidewall between the upper and bottom surfaces that is not perpendicular to the upper or bottom surface and that contains both a rough portion near the bottom surface and a smooth portion near the upper surface.

19. The device of claim 18 , wherein the angle of the sidewall angle ranges from about 10 to about 25 degrees relative to a vertical plane that is substantially perpendicular to the upper or bottom surface.

20. The device of claim 18 , wherein the sidewall comprises a concave shape near the bottom surface of the die and a straight shape near the upper surface.

21. The device of claim 18 , wherein the rough portion of the sidewall extends from about 5 to about 250 μm from the bottom surface.

22. The device of claim 21 , wherein the rough portion comprises from about 10 to about 90% of the sidewall and the smooth portion comprises about 90 to about 10%.

23. The device of claim 18 , further comprising a leadframe that is connected to the die.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2011
From: GRUENHAGEN, MIKE; DIKSHIT, ROHIT
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 026033/0755 →
Continuity (1)
Related Publication 20110062564A1 · Mar 17, 2011